Assignee: STMicroelectronics Pvt. Ltd.

Location: Uttar Pradesh, IN
No. of patents: 99

Number	Title	Issue Date
8144537	Balanced sense amplifier for single ended bitline memory architecture A balanced differential amplifier sense amplifier senses the voltage level in a selected single bit line memory cell. The output of the selected single bit-line memory cell is connected to one input of the balanced differential sense amplifier while the other input ...	03/27/2012
8108744	Locally synchronous shared BIST architecture for testing embedded memories with asynchronous interfaces A system and method of sharing testing components for multiple embedded memories and the memory system incorporating the same. The memory system includes multiple test controllers, multiple interface devices, a main controller, and a serial interface. The main contr...	01/31/2012
8055956	Built-in self-repairable memory The present invention provides a built-in self-repairable memory. The invention repairs a faulty IC through hard fuses, as well as through available redundancy in memories on chip. As the faults are not present in all the memories, the invention uses a lesser number...	11/08/2011
8046655	Area efficient memory architecture with decoder self test and debug capability An integrated test device reduces external wiring congestion to a memory. The integrated test device provides for separate decoder testing and debugging to find specific errors in the memory. The device also helps in reducing the complexity of the test of external B...	10/25/2011
7999573	Low-voltage-to-high-voltage level converter for digital signals and related integrated circuit, system, and method An embodiment of a low-to-high-level voltage translator is proposed. This translator translates the low voltage swing signals for the core into high voltage swing signals of the I/O blocks. This translator may be particularly useful for high-speed application where ...	08/16/2011
7996598	Memory management module A methodology for efficiently copying data is presented. An internal controller RAM is multiplexed between storing existing RAM data such as look up table data) and storing copy back data with respect to a flash memory. The data in the controller RAM is temporarily ...	08/09/2011
7983342	Macro-block level parallel video decoder A macro-block level parallel video decoder for a parallel processing environment is provided. The video decoder includes a Variable Length Decoding (VLD) block for decoding the encoded Discrete Cosine Transform (DCT) coefficients, a master node that receives the dec...	07/19/2011
7954017	Multiple embedded memories and testing components for the same A method of sharing testing components for multiple embedded memories and the memory system incorporating the same. The memory system includes multiple test controllers, multiple interface devices, a main controller, and a serial interface. The main controller is us...	05/31/2011
7953994	Architecture incorporating configurable controller for reducing on chip power leakage The present invention provides a method and system for controlling leakage power consumption at a System on Chip (SoC) level during a normal run or a boot-up mode. The leakage power reduction is achieved by incorporating a central programmable controller in the SoC ...	05/31/2011
7944245	Pulse filtering module circuit, system, and method A filtering module filters out high frequency signals, primarily noise, from an input data stream. The filtering module includes an input module, a phase detecting module, and a threshold module. The input module performs either a charging or a discharging across a ...	05/17/2011
7944241	Circuit for glitchless switching between asynchronous clocks A circuit for glitchless switching between asynchronous clocks includes a select circuit and enable circuits. The select circuit receives a selection signal for selecting one of the clock input signals and to generate enabling signals for activating the correspondin...	05/17/2011
7939856	Area-efficient distributed device structure for integrated voltage regulators An area efficient distributed device for integrated voltage regulators comprising at least one filler cell connected between a pair of PADS on I/O rail of a chip and at least one additional filler cell having small size replica of said device is coupled to said I/O ...	05/10/2011
7919983	Multiple output level shifter A level shifter for integrated circuits includes input stage transistors, reference stage transistors, a cascode stage coupled to the input stage and the reference stage transistors and a pair of comparators. The cascode stage generates a first cascode output and a ...	04/05/2011
7902885	Compensated output buffer for improving slew control rate The disclosure relates a compensated output buffer circuit providing an improved slew rate control and a method for minimizing the variations in the current slew rate of the buffer over process, voltage and temperature (PVT) conditions. The output buffer circuit inc...	03/08/2011
7856467	Integrated circuit including at least one configurable logic cell capable of multiplication The present invention provides an integrated circuit including at least one configurable logic cell capable of multiplication comprising an addition means for adding a first input and a partial product; a first multiplexing means for receiving a first output of said...	12/21/2010
7814385	Self programmable shared bist for testing multiple memories A built-in self-test (BIST) device tests multiple embedded memories of different characteristics. The BIST includes a BIST controller, a delay generator, multiple interface modules, and a memory wrapper. The BIST controller generates an initialization sequence and a...	10/12/2010
7801261	Clock recovery from data streams containing embedded reference clock values A method and an improved apparatus for clock recovery from data streams containing embedded reference clock values controlled clock source includes of a controllable digital fractional divider receiving a control value from digital comparator and a clock input from ...	09/21/2010
7768311	Suppressing ringing in high speed CMOS output buffers driving transmission line load An output buffer circuit for improving an output during state transitions of CMOS buffers driving transmission line loads. The circuit generates variable output impedance proportional to the load transmission line impedance. The buffer includes an output stage, such...	08/03/2010
7729155	High speed, low power, low leakage read only memory A read only memory (ROM) for providing a high operational speed with reduced leakage and low power consumption. The read only memory (ROM) includes multiple bit lines, multiple word lines, multiple column select lines and these lines are operatively coupled with mul...	06/01/2010
7714625	System and method for fast re-locking of a phase locked loop circuit A system and method for reducing the re-lock time of a phase locked loop (PLL) system, the system including a circuit having a capture control voltage module, a force control voltage module, a loop filter module, and a timer. The capture control voltage module compa...	05/11/2010
7698355	Minimal area integrated circuit implementation of a polyphase interpolation filter using coefficients symmetry A minimal area integrated polyphase interpolation filter uses a symmetry of coefficients for a channel of input data. The filter includes an input interface block for synchronizing the input signal to a first internal clock signal; a memory block for providing multi...	04/13/2010
7689839	Dynamic power management in system on chips (SOC) A system for dynamic power management in a distributed architecture system on chip, comprising a means for dynamically defining the feasibility of entering a low power mode of operation based on the status of components of the system, a means for entering or exiting...	03/30/2010
7689643	N-bit constant adder/subtractor An area efficient realization of an N-bit constant coefficient adder/subtractor implemented on FPGAs, utilizing N LUTs with single output generation capability. It includes three inputs from every LUT for addition/subtraction, without any requirement for extra logic...	03/30/2010
7656987	Phase generator for introducing phase shift in a signal A phase generator includes a phase-shift enable and disable signal generator connected to configuration bits at its first input and connected to a reset signal at its reset input for generating a control signal; the configuration bits corresponding to the phase shif...	02/02/2010
7617269	Logic entity with two outputs for efficient adder and other macro implementations An improved logic entity with two outputs for efficient adder and other macro implementations providing fast response with reduced area requirements, comprising a first lookup table for generating a first output for the carry out value for a carry-in of zero and a s...	11/10/2009
7529862	System for providing access of multiple data buffers to a data retaining and processing device An area efficient system that includes a first circuit to synchronize a clock signal and a data signal and a data retaining and processing device to receive data from said data bus to thereby generate a status signal indicating the receipt of data by said area effic...	05/05/2009
7519896	Turbo encoder and related methods A turbo encoder includes multiple interleaved parallel concatenated recursive systematic convolutional encoders wherein each recursive systematic convolutional encoder is provided with an LUT that simultaneously provides the output bit pattern as well as the next st...	04/14/2009
7514962	Configurable I2C interface A synchronous serial data two-wire communications bus that can transfer data at rates up to 100 kbit/s (standard mode), 400 kbits/s (fast mode), or 3.4 Mbit/s (high-speed mode). The load of I2C bus can vary from 10 pf to 400 pf. Data transfer on the I2C bus takes pl...	04/07/2009
7502272	Self-timing read architecture for semiconductor memory and method for providing the same A semiconductor memory device having a control circuit, decoder circuit, a dummy column, and a normal memory cell array divided in clusters of N consecutive rows, where N can be one or more than one, and for each cluster of N rows a common circuitry is used in block...	03/10/2009
7486110	LUT based multiplexers An improved LUT based multiplexer, including a first set of muxlets, each receiving a subset of input data lines at its inputs and one or more muxlet stages cascaded together to form a tree structure in which the roots are the first set of muxlets and the last stage...	02/03/2009
7483289	Synchronous SRAM capable of faster read-modify-write operation An improved synchronous SRAM capable of faster read-modify-write cycle time using separate input and output terminals. It describes the circuitry for performing a RMW operation in a memory module at high frequency in a nanometer technology. A byte write enable bus i...	01/27/2009
7475105	One bit full adder with sum and carry outputs capable of independent functionalities A one bit full adder with sum and carry outputs performs independent functions. The full adder includes at least one look up table (LUT) for implementing a sum function, and at least one carry circuit for implementing a carry/borrow function. The carry circuit inclu...	01/06/2009
7460718	Conversion device for performing a raster scan conversion between a JPEG decoder and an image memory The conversion device includes an input for receiving data corresponding to an image to be displayed. The received data is in a JPEG decoder output data format A processor is included for reconstructing and writing the image to be displayed into the image memory, in...	12/02/2008
7436235	Digital clock modulator A digital clock modulator provides a smoothly modulated clock period to reduce emitted electro-magnetic radiation (EMR). The digital clock modulator includes a plurality of delay elements connected in series and receiving as an input an unmodulated clock signal. A m...	10/14/2008
7436201	Architecture for reducing leakage component in semiconductor devices An architecture for reducing leakage component in semiconductor devices using a gated power supply is based on the supply being split into two parts. An alternate inverter is connected to a different power rail derived from the same single power rail. The power rail...	10/14/2008
7433239	Memory with reduced bitline leakage current and method for the same The memory includes a plurality of access transistors with each of the access transistors coupled to one of the wordlines at its control terminal and connected to one of the bitlines at its output terminal. A plurality of memory cells have each output coupled to an ...	10/07/2008
7418031	Automatic baud rate determination The present invention provides an electronic device consisting of a Universal Asynchronous Receiver Transmitter (UART) having its transmit data output connected to a triggered timer and a computing means that computes the transmitted baud rate from the time measured...	08/26/2008
7403433	Self timing write architecture for semiconductor memory and method for providing the same A self timing write architecture for semiconductor memory and a method for providing the same are provided. The core region of the semiconductor memory comprises of a normal memory cell array and a dummy column. The dummy column comprises of two blocks—block A and...	07/22/2008
7394638	System and method for a whole-chip electrostatic discharge protection that is independent of relative supply rail voltages and supply sequencing The embodiments of the present invention introduced and taught herein are directed to a whole-chip ESD protection arrangement that is independent of relative supply rail voltage and supply sequencing, thereby enabling ESD conduction path during ESD event and isolati...	07/01/2008
7385862	Shared redundant memory architecture and memory system incorporating same A memory system incorporates shared redundant memories and has a shared redundant memory architecture. The memory system includes a modified memory to be used as a shared redundant memory between memory systems. These memory systems may have several smaller memories...	06/10/2008

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Assignee: STMicroelectronics Pvt. Ltd.