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| Number | Title | Issue Date |
| 8151151 | Tap time division multiplexing with scan test An integrated circuit comprising (i) a plurality of portions, each portion including test control circuitry; and (ii) at least one test input arranged to receive test signals, the circuit having a test mode in which one or more of the plurality of portions are testa... | 04/03/2012 |
| 8046647 | TAP sampling at double rate An integrated circuit comprising: at least one test input for receiving test data; test control circuitry between the at least one test input and circuitry to be tested; wherein the test data is clocked in on a rising clock edge and a falling clock edge. ... | 10/25/2011 |
| 8042157 | System for restricting data access A filter is arranged to selectively block or allow a data access command from an initiator according to whether the initiator is secure or insecure and whether a data source or destination being accessed is privileged or unprivileged. The data access command contain... | 10/18/2011 |
| 7929655 | Asynchronous multi-clock system A system for controlling the transfer of a signal sequence in a first clock domain to a plurality of other clock domains. The system comprising: detecting circuitry for detecting receipt of the signals from the clock domains and setting an update signal when all of ... | 04/19/2011 |
| 7895447 | Secure processor arrangement A system and method for verifying the authenticity of instructions retrieved from a memory for execution by a processor. In one embodiment, an instruction monitor monitors execution parameters associated with the retrieved instruction and resets the system in respon... | 02/22/2011 |
| 7890628 | Method for controlling services A method and apparatus are provided for controlling services provided at a first electronic device at a second electronic device. A plurality of electronic devices connected to a network provide services in the form of providing data to the network, or allowing the ... | 02/15/2011 |
| 7889862 | Key update mechanism A memory stores data in an encrypted form. A modifiable register stores a memory address, a0, defining a boundary separating the memory into two regions. The lower region stores data encrypted using a key B, and the upper region stores data encrypted usin... | 02/15/2011 |
| 7836300 | Security integrated circuit A semiconductor integrated circuit for the processing of conditional access television signals, the circuit including an input interface for receiving encrypted television signals and an output interface for output of decrypted television signals. Control signals br... | 11/16/2010 |
| 7797438 | Processing buffered data Data reception apparatus for receiving and processing a data stream including a stream of data units, the data apparatus comprising: a buffer; a data reception controller for receiving data units from the data stream, storing received data units in the buffer, and i... | 09/14/2010 |
| 7796755 | Storage of digital data A device for locating a DES key value that corresponds to a packet identification (PID) contained at a variable possible location which comprises part only of a 32-bit packet header. A table stored in memory contains for each DES key: (i) a packet header having 32 b... | 09/14/2010 |
| 7793261 | Interface for transferring debug information An microcomputer is provided including a processor and a debug circuit including a dedicated link which transfers information between the processor and debug circuit to support debugging operations. In one aspect, the processor provides program counter information, ... | 09/07/2010 |
| 7783894 | Monolithic semiconductor integrated circuit and method for selective memory encryption and decryption A monolithic semiconductor integrated circuit is provided for selectively encrypting or decrypting data transmitted between one of a plurality of devices on the circuit and an external memory. Two series of data pathways connect the devices and the external memory. ... | 08/24/2010 |
| 7730508 | Data injection A data transport device for transporting a data stream, the device including: a data stream processing unit for receiving an input data stream including a plurality of data items, performing processing in dependence on the content of the items and forming an output ... | 06/01/2010 |
| 7720112 | Routing of data streams The routing of data streams is discussed, and particularly routing one or more incoming streams to one or more output destination ports. The ability to merge incoming streams is discussed so that several low bit rate input packet streams can be merged into a higher ... | 05/18/2010 |
| 7702974 | TAP time division multiplexing with scan test An integrated circuit comprising (i) a plurality of portions, each portion including test control circuitry; and (ii) at least one test input arranged to receive test signals, the circuit having a test mode in which one or more of the plurality of portions are testa... | 04/20/2010 |
| 7698718 | Method and system for restricting use of data in a circuit An integrated circuit restricts use of a data item and includes a data memory storing the data item; a value memory storing a value; a signature input that receives a signature derived from data in a data item field and a value in a value field, the signature being ... | 04/13/2010 |
| 7685482 | Tap sampling at double rate An integrated circuit comprising: at least one test input for receiving test data; test control circuitry between the at least one test input and circuitry to be tested; wherein the test data is clocked in on a rising clock edge and a falling clock edge. ... | 03/23/2010 |
| 7624442 | Memory security device for flexible software environment A semiconductor integrated circuit includes a processor for executing application code from a memory and a verifier processor arranged to receive the application code via the same internal bus as the processor. The verifier processor performs a verification function... | 11/24/2009 |
| 7545896 | Asynchronous multi-clock system A system for controlling the transfer of a signal sequence in a first clock domain to a plurality of other clock domains. The system comprising: detecting circuitry for detecting receipt of the signals from the clock domains and setting an update signal when all of ... | 06/09/2009 |
| 7506810 | Card detection A card reader reads data stored on a card. A contact signal is produced whose state is indicative of the presence or absence of electrical contact between the card and the card reader. A high state indicates the presence of electrical contact and a low state indicat... | 03/24/2009 |
| 7496656 | Processing instruction words A method for processing an instruction word in a data processing system, the instruction word comprising a plurality of instruction bit positions, each bit position corresponding to an instruction actions, and a status of the bit at an instruction bit position indic... | 02/24/2009 |
| 7489780 | Security integrated circuit A semiconductor integrated circuit for the processing of conditional access television signals comprises an input interface for receiving encrypted television signals and an output interface for output of decrypted television signals. Control signals broadcast with ... | 02/10/2009 |
| 7489724 | System and method for connecting a host and a target A system for controlling communications between a host and a target, the system having a data input for receiving a data signal, a clock input for receiving a clock signal, an oversampling circuit for sampling a received data signal and generating a control signal t... | 02/10/2009 |
| 7480783 | Systems for loading unaligned words and methods of operating the same Disclosed are systems for loading an unaligned word from a specified unaligned word address in a memory, the unaligned word comprising a plurality of indexed portions crossing a word boundry, a method of operating the system comprising: loading a first aligned word ... | 01/20/2009 |
| 7464129 | Circuitry for carrying out a square root operation The invention provides circuitry for carrying out a square root operation. The circuitry utilizes iteration circuitry for carrying out a plurality of iterations. The iteration circuitry includes a circuit for calculating a root multiple, the root multiple being a mu... | 12/09/2008 |
| 7406581 | Speculative instruction load control A method and system for validating speculative load operations. The system identifies speculative load operations that might be executed in a code sequence and after translating the virtual address of the speculative load to a physical address, a speculative load co... | 07/29/2008 |
| 7406113 | Integrated circuit for code acquisition A semiconductor integrated circuit for processing a plurality of received broadcast signals, such as GPS signals, is operable in two modes: acquisition and tracking. In an acquisition mode, sample reducer combines samples of a received signal for correlation with a ... | 07/29/2008 |
| 7403558 | Integrated circuit for code acquisition A semiconductor integrated circuit for processing a plurality of received broadcast signals, such as GPS signals, is operable in two modes: acquisition and tracking. In an acquisition mode, a memory arrangement comprising two circulating shift registers circulates s... | 07/22/2008 |
| 7398440 | Tap multiplexer An integrated circuit comprising: a plurality of portions, each portion including test control circuitry; at least one test input arranged to receive test signals; and a multiplexer between the at least one test input and the test control circuitry, the multiplexer ... | 07/08/2008 |
| 7395296 | Circuitry and method for performing non-arithmetic operations Circuitry is provided for performing a non-arithmetic operation in relation to at least one number. The circuitry includes a first part for carrying out the non-arithmetic operation in relation to the at least one number, the first part providing a result. A second ... | 07/01/2008 |
| 7356708 | Decryption semiconductor circuit A semiconductor integrated circuit having a plurality of selectable pathways inter-connected to data sources and data destinations; a cryptographic circuit connected to the selectable pathways to selectively receive data from at least one of the data sources, to dec... | 04/08/2008 |
| 7353508 | Method, apparatus and article for generation of debugging information Call frame information is used by debugging software. It records how to restore the parent stack frame at any point during execution of a program. It is normally generated during compilation and stored in the executable in a compressed format, consisting of sequence... | 04/01/2008 |
| 7307631 | Computer graphics An image is rendered which includes at least one light source, a first, shadow-casting object with a second, shadow-receiving object located on the side of the first shadow-casting object remote from said at least one light source. A shadow mask is generated which i... | 12/11/2007 |
| 7253816 | Computer graphics acceleration method and apparatus for evaluating whether points are inside a triangle A computer graphics accelerator apparatus and method determines whether a pixel at predetermined pixel co-ordinates in an area being rasterized is within a triangle defining a sub-area of the area. The coordinate system in relation to which the triangle is defined i... | 08/07/2007 |
| 7248602 | Flexible filtering A circuit and method for demultiplexing in a receiver a digital data stream including at least two types of data. In one particular application, such a receiver is used in a television system having a digital set-top-box receiver. A first control circuit extracts a ... | 07/24/2007 |
| 7243202 | Searching for packet identifiers A method of locating packet identifiers held in respective memory locations in a memory, the method comprising receiving a plurality of packets, each packet including a packet identifier, searching said memory locations in a sequence to compare an incoming packet id... | 07/10/2007 |
| 7216342 | Code generation A method of linking a plurality of object files to generate an executable program, the method comprises identifying in the object files at least one routine to be locked into a cache when the program is executed, locating said routine at a set of memory addresses wh... | 05/08/2007 |
| 7200843 | Retrieval of symbol attributes A method of linking a plurality of object code modules to form an executable program, each object code module having section data, a set of relocation instructions and one or more symbols, each symbol having a plurality of attributes associated therewith, wherein th... | 04/03/2007 |
| 7191416 | System and method for modifying integrated circuit hold times A method of arranging an integrated circuit to correct for hold time errors comprises fixing the position of existing cells in a design, determining hold time errors required to be corrected and placing buffer cells in spaces in the existing design. By placing buffe... | 03/13/2007 |
| 7187774 | Mute switch A mute switch including a field effect transistor receiving a mute control signal at its gate for selectively supplying an audio signal from an input node to an output node. A bipolar transistor is connected between the input node and the FET for reducing the voltag... | 03/06/2007 |
