Assignee: SRC Computers, Inc.

Location: Colorado Springs, CO
No. of patents: 26

Number	Title	Issue Date
7890686	Dynamic priority conflict resolution in a multi-processor computer system having shared resources A system and method for fair dynamic priority conflict resolution in a multi-processor computer system having shared resources wherein each multi-processor seeking access to said shared resource possesses a common priority level. In the occurrence of a priority tie ...	02/15/2011
7703085	Process for converting programs in high-level programming languages to a unified executable for hybrid computing platforms A system and method for compiling computer code written to conform to a high-level language standard to generate a unified executable containing the hardware logic for a reconfigurable processor, the instructions for a traditional processor (instruction processor), ...	04/20/2010
7680968	Switch/network adapter port incorporating shared memory resources selectively accessible by a direct execution logic element and one or more dense logic devices in a fully buffered dual in-line memory module format (FB-DIMM) An enhanced switch/network adapter port incorporating shared memory resources (“SNAPM™”) selectively accessible by a direct execution logic element and one or more dense logic devices in a fully buffered dual in-line memory module (“FB-DIMM”) format for cl...	03/16/2010
7620800	Multi-adaptive processing systems and techniques for enhancing parallelism and performance of computational functions Multi-adaptive processing systems and techniques for enhancing parallelism and performance of computational functions are disclosed which can be employed in a myriad of applications including multi-dimensional pipeline computations for seismic applications, search a...	11/17/2009
7565461	Switch/network adapter port coupling a reconfigurable processing element to one or more microprocessors for use with interleaved memory controllers A switch/network adapter port (“SNAP™”) in a dual in-line memory module (“DIMM”) or Rambus™ in-line memory module (“RIMM”) format for clustered computers employing multi-adaptive processor (“MAP®”, both trademarks of SRC Computers, Inc.) element...	07/21/2009
7424552	Switch/network adapter port incorporating shared memory resources selectively accessible by a direct execution logic element and one or more dense logic devices An enhanced switch/network adapter port (“SNAP™”) including collocated shared memory resources (“SNAPM™”) in a dual in-line memory module (“DIMM”) or any other memory module format for clustered computing systems employing direct execution logic such...	09/09/2008
7421524	Switch/network adapter port for clustered computers employing a chain of multi-adaptive processors in a dual in-line memory module format A switch/network adapter port (“SNAP”) for clustered computers employing multi-adaptive processor (“MAP™”, a trademark of SRC Computers, Inc.) elements in a dual in-line memory module (“DIMM”) or Rambus™ in-line memory module (“RIMM”) format to s...	09/02/2008
7406573	Reconfigurable processor element utilizing both coarse and fine grained reconfigurable elements A reconfigurable processor element incorporating both course and fine grained reconfigurable elements. In alternative implementations, the present invention may comprise a reconfigurable processor comprising both reconfigurable devices with fine grained logic elemen...	07/29/2008
7373440	Switch/network adapter port for clustered computers employing a chain of multi-adaptive processors in a dual in-line memory module format A switch/network adapter port (“SNAP”) for clustered computers employing multi-adaptive processor (“MAP™”, a trademark of SRC Computers, Inc.) elements in a dual in-line memory module (“DIMM”) or Rambus™ in-line memory module (“RIMM”) format to s...	05/13/2008
7299458	System and method for converting control flow graph representations to control-dataflow graph representations An embodiment of the invention includes a method of forming a control-dataflow graph that includes separating a control flow graph into two or more basic blocks, and converting said two or more basic blocks into code blocks, where the code blocks are formed into the...	11/20/2007
7237091	Multiprocessor computer architecture incorporating a plurality of memory algorithm processors in the memory subsystem A multiprocessor computer architecture incorporating a plurality of programmable hardware memory algorithm processors (“MAP”) in the memory subsystem. The MAP may comprise one or more field programmable gate arrays (“FPGAs”) which function to perform identif...	06/26/2007
7225324	Multi-adaptive processing systems and techniques for enhancing parallelism and performance of computational functions Multi-adaptive processing systems and techniques for enhancing parallelism and performance of computational functions are disclosed which can be employed in a myriad of applications including multi-dimensional pipeline computations for seismic applications, search a...	05/29/2007
7197575	Switch/network adapter port coupling a reconfigurable processing element to one or more microprocessors for use with interleaved memory controllers A switch/network adapter port (“SNAP™”) in a dual in-line memory module (“DIMM”) or Rambus™ in-line memory module (“RIMM”) format for clustered computers employing multi-adaptive processor (“MAP®”, both trademarks of SRC Computers, Inc.) element...	03/27/2007
7167976	Interface for integrating reconfigurable processors into a general purpose computing system The present invention describes a method and system for an interface for integrating reconfigurable processors into a general purpose computing system. In particular, the system resides in a computer system containing standard instruction processors, as well as reco...	01/23/2007
7155602	Interface for integrating reconfigurable processors into a general purpose computing system The present invention describes a method and system for an interface for integrating reconfigurable processors into a general purpose computing system. In particular, the system resides in a computer system containing standard instruction processors, as well as reco...	12/26/2006
7155708	Debugging and performance profiling using control-dataflow graph representations with reconfigurable hardware emulation An embodiment of the invention includes a method of simulating a hybrid instruction processor and reconfigurable processor implemented algorithm which utilizes a runtime selectable emulation library that emulates a reconfigurable processor and its resources, and a c...	12/26/2006
7149867	System and method of enhancing efficiency and utilization of memory bandwidth in reconfigurable hardware A reconfigurable processor that includes a computational unit and a data prefetch unit coupled to the computational unit, where the data prefetch unit retrieves data from a memory and supplies the data to the computational unit through memory and a data access unit,...	12/12/2006
7134120	Map compiler pipelined loop structure A control-flow dataflow graph pipelined loop structure that includes a loop body that processes an input value to generate an output value in successive iterations of the loop body, where the output value is captured by a circulate node coupled to the loop body, a l...	11/07/2006
7124211	System and method for explicit communication of messages between processes running on different nodes in a clustered multiprocessor system Embodiments of the invention include a mechanism for explicit communication in a clustered multiprocessor system that supports low-latency, protected, user-mode, communication across the machine boundaries of a clustered multiprocessor. Data transport may be accompl...	10/17/2006
7003593	Computer system architecture and memory controller for close-coupling within a hybrid processing system utilizing an adaptive processor interface port A computer system architecture and memory controller for close-coupling within a hybrid computing system using an adaptive processor interface port (“APIP”) added to, or in conjunction with, the memory and I/O controller chip of the core logic. Memory accesses t...	02/21/2006
6996656	System and method for providing an arbitrated memory bus in a hybrid computing system A computing system having at least one microprocessor and a memory subsystem coupled to the at least one microprocessor. A memory controller is coupled to manage memory transactions between the memory subsystem and the at least one microprocessor. At least one arbit...	02/07/2006
6983456	Process for converting programs in high-level programming languages to a unified executable for hybrid computing platforms A system and method for compiling computer code written to conform to a high-level language standard to generate a unified executable containing the hardware logic for a reconfigurable processor, the instructions for a traditional processor (instruction processor), ...	01/03/2006
6964029	System and method for partitioning control-dataflow graph representations An embodiment of the invention includes a system for partitioning a control-flow graph representation into a reconfigurable portion and an instruction processor portion. Another embodiment of the invention includes a method of partitioning a control-dataflow graph r...	11/08/2005
6961841	Multiprocessor computer architecture incorporating a plurality of memory algorithm processors in the memory subsystem A multiprocessor computer architecture incorporating a plurality of programmable hardware memory algorithm processors (“MAP”) in the memory subsystem. The MAP may comprise one or more field programmable gate arrays (“FPGAs”) which function to perform identif...	11/01/2005
6941539	Efficiency of reconfigurable hardware The present invention includes a method of computing a function array in reconfigurable hardware that includes forming in the reconfigurable hardware a first delay queue and a second delay queue, inputting from a source array outside the reconfigurable hardware a fi...	09/06/2005
6836823	Bandwidth enhancement for uncached devices A system and method for enhancing the utilization of available bandwidth for an uncached device. Data written to the device is done so by striding the available data into multiple data elements of the appropriate size for the uncached device. Data read from the devi...	12/28/2004

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Assignee: SRC Computers, Inc.