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Assignee: Renesas Electronics Corporation


Location: JP
No. of patents: 6

NumberTitleIssue Date
8416330Solid state imaging device for imaging an object placed thereon
The solid state image pick-up device comprises a chip wherein an object to be photographed is put directly on the back surface of the chip, a light incident on the object enters the inner portion of the chip, signal electric charges generated in the inner portion of...
04/09/2013
8324718Warp-suppressed semiconductor device
A semiconductor device includes: a semiconductor chip mounted on a mounting substrate; a first resin filling a gap between the chip and the substrate; a frame-shaped stiffener surrounding the chip; a first adhesive for bonding the stiffener to the substrate; a lid f...
12/04/2012
8233063Solid state image pick-up device for imaging an object placed thereon
The solid state image pick-up device comprises a chip wherein an object to be photographed is put directly on the back surface of the chip, a light incident on the object enters the inner portion of the chip, signal electric charges generated in the inner portion of...
07/31/2012
8188566Semiconductor integrated circuit device
The bottom side of an N type silicon substrate is connected to a power supply terminal, a second P type epitaxial layer is formed on all sides of the N type silicon substrate, and a device forming portion is provided on the second P type epitaxial layer. A first P t...
05/29/2012
7974457Method and program for correcting and testing mask pattern for optical proximity effect
A method of testing a mask pattern, includes applying optical proximity-effect compensation to a first pattern to be tested and to be formed onto a mask layer, to thereby form a mask pattern of the mask layer, dividing the first pattern into a plurality of areas in ...
07/05/2011
7973383Semiconductor integrated circuit device having a decoupling capacitor
The bottom side of an N type silicon substrate is connected to a power supply terminal, a second P type epitaxial layer is formed on all sides of the N type silicon substrate, and a device forming portion is provided on the second P type epitaxial layer. A first P t...
07/05/2011
 
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