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| Number | Title | Issue Date |
| 8165251 | Interpolation IIR filter for OFDM baseband processing A filter for receiver and operative on a stream of OFDM symbols has a symbol timing identifier which indicates the time interval for each symbol and also indicates a non-truncation interval and a truncation interval of the stream of symbols. The stream of OFDM symbo... | 04/24/2012 |
| 8161205 | Packet buffer management apparatus and method A reduced complexity maximum likelihood decoder receives a stream of received symbols Y accompanied by a channel estimate matrix H. A variable transformation part includes a first part which converts Y and H into Z and R by computing a matrix R having at least one n... | 04/17/2012 |
| 8160190 | IIR receive filter for OFDM baseband processor A receive filter for a stream of OFDM symbols has an infinite impulse response (IIR) filter which receives packets having a preamble part followed by a data part, the data part having a succession of cyclic prefixes followed by OFDM symbols. The packet is provided t... | 04/17/2012 |
| 8155220 | IIR transmit filter for OFDM baseband processor A transmit filter for a stream of OFDM symbols has a remapper, Infinite Impulse Response (IIR) filter and a controller, the transmit filter operating on a stream of OFDM symbols. The transmit filter accepts symbols to be transmitted, the re-mapper re-orders them, th... | 04/10/2012 |
| 8151155 | Packet Re-transmission controller for block acknowledgement in a communications system A re-transmit processor for a wireless communication system includes a pointer memory which contains pointers associated with particular packet data in a host memory. The re-transmit processor directs data associated with the pointers to be applied to a media access... | 04/03/2012 |
| 8149966 | Packet acquisition controller with signal strength threshold control for wireless MIMO receiver An packet detection controller accepts an input from an AGC controller which indicates the presence of an increased signal energy and also completion of an AGC process and generates an output to suspend the AGC process. The packet detection controller also receives ... | 04/03/2012 |
| 8149965 | Level sensitive packet detector An packet detection controller accepts an input from an AGC controller which indicates the presence of an increased signal energy and also completion of an AGC process and generates an output to suspend the AGC process. The packet detection controller also receives ... | 04/03/2012 |
| 8139699 | Process for preamble detection in a multi-stream 802.16E receiver A preamble detector for a plurality of streams of baseband digitized signals has a plurality of preamble processors, each preamble processor coupled to an input and generating an output. Each preamble processor has an input coupled to a first delay, the output of th... | 03/20/2012 |
| 8090062 | Process for packet detection An packet detection controller accepts an input from an AGC controller which indicates the presence of an increased signal energy and also completion of an AGC process and generates an output to suspend the AGC process. The packet detection controller also receives ... | 01/03/2012 |
| 8090035 | Method for setting inter-packet gain An packet detection controller accepts an input from an AGC controller which indicates the presence of an increased signal energy and also completion of an AGC process and generates an output to suspend the AGC process. The packet detection controller also receives ... | 01/03/2012 |
| 8081700 | Power allocation method for MIMO transmit beamforming A transmit power allocation method for computing a transmit beamforming W matrix for a N streams of data, the method has a first step of measuring a receive channel characteristic H matrix, a second step of decomposing the H matrix into a U matrix which is formed fr... | 12/20/2011 |
| 8077591 | Combined OFDMA preamble index identification, integer frequency offset estimation, and preamble CINR measurement A wireless signal processor for use in identifying a maximum Carrier to Noise Interference Ratio (CINR) associated with a plurality of received OFDMA subcarriers has a candidate generator for forming a plurality of candidate values from a particular set of received ... | 12/13/2011 |
| 8073085 | Analog to digital converter bit width and gain controller for a wireless receiver A gain controller for a wireless communication system sets the receiver gain during the initial time duration of a preamble, and for each subsequent symbol computes a new gain value, which is applied at the end of each symbol. An analog to digital converter resoluti... | 12/06/2011 |
| 8051222 | Concatenating secure digital input output (SDIO) interface An apparatus and a process for transferring packet data includes receiving packets from a first interface such as a network interface and transferring data to a second interface such as an SD Bus interface such as SDIO using a protocol such as one described in SDCar... | 11/01/2011 |
| 8031762 | Stream weight estimation and compensation in SIMO/MIMO OFDM receivers A process for equalizing streams of OFDM subcarrier data computes the noise variance for each stream, and forms a stream weighting coefficient by equalizing the noise variance, such that for a first stream having a noise variance σ1 and a second stream h... | 10/04/2011 |
| 8008949 | Clock selection for a communications processor having a sleep mode A clock selector operative on two clocks operating on different domains and responsive to a SELECT input provides a transition from a first clock to a second clock, and from a second clock to a first clock with a dead zone therebetween. The delay is provided by a do... | 08/30/2011 |
| 8005179 | Preamble detection in a multi-antenna MIMO 802.16e receiver A preamble detector for a plurality of streams of baseband digitized signals has a plurality of preamble processors, each preamble processor coupled to an input and generating an output. Each preamble processor has an input coupled to a first delay, the output of th... | 08/23/2011 |
| 7965782 | Reduced complexity maximum likelihood decoder for MIMO communications A reduced complexity maximum likelihood decoder receives a stream of symbols Y and channel estimate H. A transformation converts Y and H into Z and R by computing matrix R, such that the product of R and Q produces matrix H. A second transformation column-swaps matr... | 06/21/2011 |
| 7957273 | Packet re-transmission controller for block acknowledgement in a communications system A re-transmit processor for a wireless communication system includes a pointer memory which contains pointers associated with particular packet data in a host memory. The re-transmit processor directs data associated with said pointers to be applied to a media acces... | 06/07/2011 |
| 7936237 | Multi-band transmit-receive switch for wireless transceiver A transmit-receive switch has a transmit port, an antenna port, and a receive port. A first switch couples the transmit port to the antenna port when a signal TxON is asserted. A LOW_BAND signal indicates the selection of a lower band of frequencies. A tuning struct... | 05/03/2011 |
| 7907555 | RSSI-based powerdown apparatus and method for a wireless communications system A wireless receiver generates quadrature baseband signals which are sampled by a high speed analog to digital converter (IQ ADC) and also uses a receive signal strength indicator (RSSI) which is sampled by an RSSI analog to digital converter (RSSI ADC). The RSSI ADC... | 03/15/2011 |
| 7870468 | Reed-solomon decoder using a configurable arithmetic processor A Reed Solomon decoder utilizes re-configurable and re-usable components in a granular configuration which provides an upper array and a lower array of repeated Reconfigurable Elementary Units (REU) which in conjunction with a FIFO can be loaded with syndromes and c... | 01/11/2011 |
| 7844007 | Combined OFDMA preamble index identification, integer frequency offset estimation, and preamble CINR measurement A wireless signal processor for use in identifying a maximum Carrier to Noise Interference Ratio (CINR) associated with a plurality of received OFDMA subcarriers has a candidate generator for forming a plurality of candidate values from a particular set of received ... | 11/30/2010 |
| 7761688 | Multiple thread in-order issue in-order completion DSP and micro-controller An in-order issue in-order completion micro-controller comprises a pipeline core comprising in succession a fetch address stage, a program access stage, a decode stage, a first execution stage, a second execution stage, a memory access stage, and a write back stage.... | 07/20/2010 |
| 7657683 | Cross-thread interrupt controller for a multi-thread processor An interrupt controller for a dual thread processor has for a first thread, an interrupt request register accessible to the second thread, an interrupt count accessible to the second thread, and an interrupt acknowledge accessible to the first thread. Additionally, ... | 02/02/2010 |
| 7656970 | Apparatus for a wireless communications system using signal energy to control sample resolution and rate A wireless signal processor includes an analog front end for generating at least one baseband analog signal, at least one analog to digital converter for converting the baseband signal into a digital signal, the analog to digital converter having a resolution width ... | 02/02/2010 |
| 7634000 | Noise estimator for a communications system A SINR estimator receiving a symbol stream has a delay element coupled to the symbol stream to produce a delayed symbol stream, which is also coupled to a conjugator. A first multiplier forms a product from the symbol stream and the output of the conjugator, thereaf... | 12/15/2009 |
| 7593459 | Wireless link simulator A wireless link simulator includes, in sequence, a digital transmit device under test (TX-DUT), a wireless link simulator, and a digital receive device under test (RX-DUT). The wireless link simulator includes, in sequence, a transmitter IQ imbalance generator, a po... | 09/22/2009 |
| 7593378 | SINR-based powerdown apparatus and method for a wireless communications systems During the preamble interval of a wireless packet, a receiver estimates the SINR of the preamble, and also examines the packet header to determine the data rate, length, and destination address. If the SINR as determined from the preamble is below a threshold, or if... | 09/22/2009 |
| 7529865 | Packet buffer management apparatus and method A memory controller for a wireless communication system comprises a packet buffer write system and a packet buffer read system. The packet buffer write system places packets including packet header and packet data into a packet buffer. The packet buffer read system ... | 05/05/2009 |
| 7464201 | Packet buffer management apparatus and method A memory controller for a wireless communication system comprises a packet buffer write system and a packet buffer read system. The packet buffer write system places packets including packet header and packet data into a packet buffer. The packet buffer read system ... | 12/09/2008 |
| 7450911 | Multiplexed wireless receiver and transmitter A baseband receiver having quadrature analog outputs and a plurality of analog control and status signals and a transmit modulator having analog quadrature inputs and a plurality of analog control and status signals are coupled to a transmit processor having a digit... | 11/11/2008 |
| 7412000 | Maximum likelihood block decision feedback estimation for CCK demodulation apparatus and method A maximum likelihood CCK detector has a first subtractor which subtracts the contents of a pre-equalize register from a current symbol, and the output of this subtractor is coupled to a simple Fast Walsh Transform (FWT) with an iteration variable k. The output of th... | 08/12/2008 |
| 7386074 | Digital automatic gain control method and apparatus An RF receiver which produces quadrature digitized outputs and has a gain control is coupled to a digital gain controller which converts the quadrature digitized outputs into an rms voltage, and iterates over a finite number of steps to quickly control the gain to a... | 06/10/2008 |
| 7327700 | Flexible multi-channel multi-thread media access controller and physical layer interface for wireless networks A wireless signal processor for handling a plurality of wireless sessions comprises a plurality of baseband receivers, one for each session, each receiver producing a digital output, a multiplexer for multiplexing the plurality of digital outputs into a single data ... | 02/05/2008 |
| 7298772 | Packet detection, symbol timing, and coarse frequency estimation in an OFDM communications system A integrated system for generation of packet detection, symbol timing, and coarse frequency offset for an orthogonal frequency division multiplexed (OFDM) receiver having a stream of input symbols applied comprises a first multiplier performing a multiplication on a... | 11/20/2007 |
| 7298799 | All-tap fractionally spaced, serial rake combiner apparatus and method A decision processor for 802.11b codewords for 1 Mb and 2 Mb data rates includes a sliding correlator for the acquisition of correlation peaks. During a training interval, these correlation peaks are summed into a channel profile memory. The correlation peaks corres... | 11/20/2007 |
| 7296100 | Packet buffer management apparatus and method A memory controller for a wireless communication system comprises a packet buffer write system and a packet buffer read system. The packet buffer write system places packets including packet header and packet data into a packet buffer. The packet buffer read system ... | 11/13/2007 |
| 7295144 | Quantizer responsive to noise level for a wireless communications system A quantizer has a plurality of decision blocks, each coupled from input to output, where each decision blocks output generates a binary value that is an unchanged decision block input if the decision block input is below the threshold input level divided by a power ... | 11/13/2007 |
| 7218896 | Multiplexed wireless receiver and transmitter A baseband receiver having quadrature analog outputs and a plurality of analog control and status signals and a transmit modulator having analog quadrature inputs and a plurality of analog control and status signals are coupled to a transmit processor having a digit... | 05/15/2007 |
