Assignee: Rambus, Inc.

Location: Los Altos, CA
No. of patents: 22

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Number	Title	Issue Date
8036300	Dual loop clock recovery circuit A clock recovery circuit for digital data transmission includes a delay lock loop having a first loop which generates a phase difference signal which is indicative of a quantized phase difference between a data signal and a clock signal; and a second loop which gene...	10/11/2011
7917727	Data processing architectures for packet handling using a SIMD array An input/output system transfers data packets to and from a SIMD array of processing elements (PEs) such that different sizes of data packets are transferred to respective ones of the PEs. The packets are transferred in batches to respective different addresses in t...	03/29/2011
7812653	Power supply noise rejection in PLL or DLL circuits A phase controller can be part of a phase-locked loop (PLL) or a delay-locked loop (DLL). The phase controller includes first and second regulators. The first regulator provides power supply noise rejection while the second regulator provides phase and frequency loc...	10/12/2010
7808937	Variable interference cancellation technology for CDMA systems An interference canceller comprises a composite interference vector (CIV) generator configured to produce a CIV by combining soft and/or hard estimates of interference, an interference-cancelling operator configured for generating a soft-projection operator, and a s...	10/05/2010
7769942	Cross-threaded memory system In a data processing system, a buffer integrated-circuit (IC) device includes multiple control interfaces, multiple memory interfaces and switching circuitry to couple each of the control interfaces concurrently to a respective one of the memory interfaces in accord...	08/03/2010
7768297	Multi-drop bus system A multi-drop bus system and a method for operating such a system. The system includes a multi-drop bus having at least one bus line, each bus line being made up of a multiple of line segments. Each of the line segments terminates at a drop point and each drop point ...	08/03/2010
7735037	Generating interface adjustment signals in a device-to-device interconnection system Described are a system and method to control interface timing and/or voltage operations of signals transmitted between devices. A processor may be coupled through one or more bus interfaces of a bus to one or more corresponding interface timing and/or voltage compar...	06/08/2010
7733941	Inter-symbol interference cancellation for wireless multiple access An interference-canceling receiver is configured for cancelling inter-symbol interference due to both inter- and intra-channel interference in coded, multiple-access, spread spectrum transmissions that propagate through frequency-selective communication channels. Th...	06/08/2010
7715501	Partial response receiver A receive circuit for receiving a signal transmitted via an electric signal conductor. A first sampling circuit generates a first sample value that indicates whether the signal exceeds a first threshold level, and a second sampling circuit generates a second sample ...	05/11/2010
7715471	Signaling system with selectively-inhibited adaptive equalization An integrated circuit having a receiver that selectively inhibits incoming data from being used to update adaptively generated controls. Sampling circuitry generates a plurality of samples of an incoming signal. Control circuitry generates an inhibit signal in eithe...	05/11/2010
7711063	Digital transmitter with data stream transformation circuitry A transmitter with data stream transformation circuitry is described. The transmitter has a first driver and a second driver. Each driver has an output for a respective analog signal. A summation circuit combines respective analog signals from the first driver and t...	05/04/2010
7683680	Combined phase comparator and charge pump circuit A phase comparison of timing signals is made by combinational circuitry which receives the timing signals and a window signal, the window signal identifying edges of the timing signals to be compared. The comparison may result in a charge pumped output which can be ...	03/23/2010
7663966	Single-clock, strobeless signaling system A signaling system includes a signaling path, a master device coupled to the signaling path, a slave device coupled to the signaling path, and a clock generator. The slave device includes timing circuitry to generate an internal clock signal having a phase offset re...	02/16/2010
7640448	Drift tracking feedback for communication channels A communication channel includes a first component having a transmitter coupled to a normal signal source, and a second component having a receiver coupled to a normal signal destination. A communication link couples the first and second components. Calibration logi...	12/29/2009
7587012	Dual loop clock recovery circuit A clock recovery circuit for digital data transmission includes a delay lock loop having a first loop which generates a phase difference signal which is indicative of a quantized phase difference between a data signal and a clock signal; and a second loop which gene...	09/08/2009
7546390	Integrated circuit device and signaling method with topographic dependent equalization coefficient An integrated circuit device includes a transmitter circuit having an output driver to output data, and a register to store a value representative of an equalization co-efficient setting of the output driver. The value may be determined based on information stored i...	06/09/2009
7535958	Hybrid wired and wireless chip-to-chip communications A hybrid wireless and wired system distributes precise timing and synchronization information among the nodes over a wired interconnect structure while data is transmitted wirelessly using ultra-wideband radio over short distances. The timing information communicate...	05/19/2009
7526664	Drift tracking feedback for communication channels A communication channel includes a first component having a transmitter coupled to a normal signal source, and a second component having a receiver coupled to a normal signal destination. A communication link couples the first and second components. Calibration logi...	04/28/2009
7519844	PVT drift compensation A timing circuit for generating a timing signal having a predetermined relationship with a reference signal. The timing circuit includes a locked loop for generating the recovered clock signal, comparing the phase of the reference signal to the phase of the timing s...	04/14/2009
7516029	Communication channel calibration using feedback A method for calibrating a communication channel coupling first and second components includes transmitting a data signal from the first component to the second component on the communication channel, and sensing a characteristic, such as phase, of the data signal o...	04/07/2009
7501867	Power supply noise rejection in PLL or DLL circuits A phase controller can be part of a phase-locked loop (PLL) or a delay-locked loop (DLL). The phase controller includes first and second regulators. The first regulator provides power supply noise rejection while the second regulator provides phase and frequency loc...	03/10/2009
7489739	Method and apparatus for data recovery A method for recovering data includes oversampling an input data signal to provide sample sets, and storing a plurality of sample sets in addressable memory. The sample sets are processed, using sequential logic to make determinations of respective samples suitable ...	02/10/2009

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Assignee: Rambus, Inc.