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| Number | Title | Issue Date |
| 8082528 | Process-independent schema library Methods are provided for utilizing a process-independent schema library that contains all the devices and all the device parameters in each of various process-specific schema libraries that a user or a group of users is working with. A process-specific schematic bas... | 12/20/2011 |
| RE42785 | Semiconductor module with serial bus connection to multiple dies A semiconductor module is provided which includes a beat heat spreader, at least two semiconductors thermally coupled to the heat spreader, and a plurality of electrically conductive leads electrically connected to the semiconductors. At least one of the electricall... | 10/04/2011 |
| 8018789 | Methods and systems for reducing heat flux in memory systems The memory module includes front and back faces. Multiple devices are disposed on each of the faces. A first control line serially connects a first group of devices on both the front and back faces so that the first group of devices commonly contribute multiple bits... | 09/13/2011 |
| 7989265 | Process for making a semiconductor system having devices that have contacts on top and bottom surfaces of each device Multiple devices, including a first device and a second device, have operational circuitry and opposing first and second surfaces. First and second electrical contacts are formed at the first surface, while a third electrical contact is formed at the second surface ... | 08/02/2011 |
| 7958332 | Parallel data processing apparatus A controller operable to control an array of processing elements comprises a retrieval unit operable to retrieve instruction items for each of a plurality of instructions streams, each instruction stream having a plurality of instructions items, a combining unit ope... | 06/07/2011 |
| RE42429 | Semiconductor module with serial bus connection to multiple dies A semiconductor module is provided which includes a beat heat spreader, at least two semiconductors thermally coupled to the heat spreader, and a plurality of electrically conductive leads electrically connected to the semiconductors. At least one of the electricall... | 06/07/2011 |
| RE42318 | Semiconductor module with serial bus connection to multiple dies A semiconductor module is provided which includes a beat heat spreader, at least two semiconductors thermally coupled to the heat spreader, and a plurality of electrically conductive leads electrically connected to the semiconductors. At least one of the electrical... | 05/03/2011 |
| 7925861 | Plural SIMD arrays processing threads fetched in parallel and prioritized by thread manager sequentially transferring instructions to array controller for distribution A data processor comprises a plurality of processing elements arranged in a first plurality of single instruction multiple data (SIMD) processing arrays, and comprises a second plurality of controllers for transferring instructions to the processing arrays. Each con... | 04/12/2011 |
| 7890733 | Processor memory system A data processor comprises a plurality of processing elements (PEs), with memory local to at least one of the processing elements, and a data packet-switched network interconnecting the processing elements and the memory to enable any of the PEs to access the memory... | 02/15/2011 |
| 7848156 | Early read after write operation memory device, system and method A memory device, system and method for allowing an early read operation after one or more write operations is provided according to an embodiment of the present invention. The memory device comprises an interface for providing a first write address, a first write da... | 12/07/2010 |
| 7856543 | Data processing architectures for packet handling wherein batches of data packets of unpredictable size are distributed across processing elements arranged in a SIMD array operable to process different respective packet protocols at once while executing a single common instruction stream A data processing architecture comprising: an input device for receiving an incoming stream of data packets; and a plurality of processing elements which are operable to process data received thereby; ... | 12/21/2010 |
| 7853837 | Memory controller and method for operating a memory controller having an integrated bit error rate circuit A system, among other embodiments, includes a memory controller having an integrated BER circuit and a plurality of memory devices. The memory controller also includes a control circuit and an interface having at least one transmit circuit to provide write data to a... | 12/14/2010 |
| 7844023 | Phase offset cancellation for multi-phase clocks A system for use with a multi-phase clock generator is disclosed. It should also be understood that the multiphase clock generator can be a phase lock loop (PLL), delay lock loop (DLL), or any other circuit capable of providing a multiphase clock. The system compris... | 11/30/2010 |
| 7843951 | Packet storage system for traffic handling Variable size incoming data packets are queued by generating from each data packet a record portion of predetermined fixed size and containing information about the packet. Data portions of the packets are stored in independent memory locations in a first memory whi... | 11/30/2010 |
| 7836378 | System to detect and identify errors in control information, read data and/or write data An integrated circuit, such as an integrated circuit memory or buffer device, method and system, among other embodiments, generate a plurality of error codes, such as CRC codes, corresponding to control information, write data and read data transactions, respectivel... | 11/16/2010 |
| 7831888 | Unidirectional error code transfer method for a bidirectional data link A controller includes a link interface that is to couple to a first link to communicate bi-directional data and a second link to transmit unidirectional error-detection information. An encoder is to dynamically add first error-detection information to at least a por... | 11/09/2010 |
| 7831882 | Memory system with error detection and retry modes of operation A memory system includes a link having at least one signal line and a controller. The controller includes at least one transmitter coupled to the link to transmit first data, and a first error protection generator coupled to the transmitter. The first error protecti... | 11/09/2010 |
| 7830735 | Asynchronous, high-bandwidth memory component using calibrated timing elements Disclosed herein are embodiments of an asynchronous memory device that use internal delay elements to enable memory access pipelining. In one embodiment, the delay elements are responsive to an input load control signal, and are calibrated with reference to periodic... | 11/09/2010 |
| 7826516 | Iterative interference canceller for wireless multiple-access systems with multiple receive antennas This invention teaches to the details of an interference canceling receiver for canceling intra-cell and inter-cell interference in coded, multiple-access, spread spectrum transmissions that propagate through frequency selective communication channels to a multiplic... | 11/02/2010 |
| 7821519 | Scalable unified memory architecture A memory architecture includes a memory controller coupled to multiple modules. Each module includes a computing engine coupled to a shared memory. Each computing engine is capable of receiving instructions from the memory controller and processing the received inst... | 10/26/2010 |
| 7818357 | Systems and methods for implementing CORDIC rotations for projectors and related operators A CORDIC processor is configured to perform orthogonal or oblique CORDIC projections in order to cancel interference in a received signal. The CORDIC projection can be used to rotate an interference signal vector so that its only non-zero component is in the last Eu... | 10/19/2010 |
| 7817767 | Processor-controlled clock-data recovery A processor-controlled clock-data recovery (CDR) system. Phase error signals having either a first state or a second state are generated within the CDR system according to whether a first clock signal leads or lags transitions of a data signal. A difference value is... | 10/19/2010 |
| 7817743 | Multi-tone system with oversampled precoders A multi-tone system includes a data transmission circuit with an interface for receiving a data stream for transmission, a data steam splitter that splits the data stream to produce multiple substreams and a plurality of parallel data preparation circuits. Each data... | 10/19/2010 |
| 7809088 | Multiphase receiver with equalization A multiphase receiver to compensate for intersymbol interference in the sampling of an input signal includes a first integrating receiver to integrate and sample data of the input signal on a first phase of a clock and a second integrating receiver to integrate and ... | 10/05/2010 |
| 7808278 | Driver calibration methods and circuits Described are amplifiers that facilitate high-speed communication with calibrated drive strength and termination impedance. Drivers and termination elements can be divided into a number N of parallel portions, one or more of which can be disabled and updated without... | 10/05/2010 |
| 7808092 | Semiconductor device with a plurality of ground planes A multi-chip module (MCM) with a plurality of ground planes/layers is provided. Each integrated circuit (IC) chip of the MCM has its own ground plane on a substrate in the MCM. This MCM structure may facilitate separate testing of each IC chip without affecting othe... | 10/05/2010 |
| 7802212 | Processor controlled interface Described are a system and method to control interface timing and/or voltage operations of signals transmitted between devices. A processor may be coupled through one or more bus interfaces of a bus to one or more corresponding interface timing and/or voltage compar... | 09/21/2010 |
| 7793039 | Interface for a semiconductor memory device and method for controlling the interface A semiconductor memory device includes a memory core, a first interface to receive write data from a first set of interconnect resources, and a second interface, separate from the first interface, to receive from a second set of interconnect resources a column addre... | 09/07/2010 |
| 7787572 | Advanced signal processors for interference cancellation in baseband receivers A multi-mode receiver includes a channel decomposition module (e.g., a Rake receiver) for separating a received signal into multipath components, an interference selector for selecting interfering paths and subchannels, a synthesizer for synthesizing interference si... | 08/31/2010 |
| 7787518 | Method and apparatus for selectively applying interference cancellation in spread spectrum systems The present invention is directed to the selective provision of interference canceled signal streams to demodulating fingers in a communication receiver. According to the present invention, potential interferer signal paths are identified. Signal streams having one ... | 08/31/2010 |
| 7786816 | Phase controlled oscillator circuit with input signal coupler An oscillating signal in an oscillator is caused to phase shift toward the phase of an input signal coupled to the oscillating signal. The resonant frequency of the oscillator is about equal to an integer multiple of the frequency of the input signal. The input sign... | 08/31/2010 |
| 7782138 | Signaling system with low-power automatic gain control An integrated circuit device includes a variable-gain amplifier, memory circuit and gain control update circuit. The variable-gain amplifier generates an amplified signal having an amplitude according to a gain control value that is stored, at least during a first i... | 08/24/2010 |
| 7782082 | Memory-module buffer with on-die termination In memory module having multiple data inputs to couple to signal lines of an external data path, multiple memory integrated-circuits (ICs) and a buffer IC, the buffer IC includes respective interfaces coupled to the data inputs and the memory ICs, a first terminatio... | 08/24/2010 |
| 7779311 | Testing and recovery in a multilayer device Disclosed are systems and methods of producing electronic devices including an auxiliary circuit mounted on another, underlying, circuit at the wafer level. The auxiliary circuit is electrically connected to the underlying circuit via micro-scale interconnects. The ... | 08/17/2010 |
| 7772876 | Configurable on-die termination Described are systems that employ configurable on-die termination elements that allow users to select from two or more termination topologies. One topology is programmable to support rail-to-rail or half-supply termination. Another topology selectively includes fixe... | 08/10/2010 |
| 7768847 | Programmable memory repair scheme The present disclosure provides semiconductor devices and methods, systems, and apparatus for testing and operating the same. A semiconductor memory device includes data storage elements and a repair circuit. The data storage elements include primary data storage el... | 08/03/2010 |
| 7765074 | Circuit, apparatus and method for capturing a representation of a waveform from a clock-data recovery (CDR) unit A circuit, apparatus and method obtains system margin at the receive circuit using phase shifted data sampling clocks while allowing the CDR to remain synchronized with the incoming data stream in embodiments. In an embodiment, a circuit includes first and second sa... | 07/27/2010 |
| 7764095 | Clock distribution network supporting low-power mode A clock distribution network locks a local clock signal to a reference clock signal using a first feedback loop associated with a synchronization circuit (e.g., a PLL or a DLL). The local clock signal can then be selectively distributed to a plurality of clock desti... | 07/27/2010 |
| 7755968 | Integrated circuit memory device having dynamic memory bank count and page size An integrated circuit memory device has a storage array with an adjustable number of memory banks, a row of sense amplifiers to access storage cells in the storage array; and memory access control circuitry. The memory access control circuitry provides a first numbe... | 07/13/2010 |
| 7741868 | Calibration methods and circuits to calibrate drive current and termination impedance Described are on-die termination (ODT) systems and methods that facilitate high-speed communication between a driver die and a receiver die interconnected via one or more signal transmission lines. An ODT control system in accordance with one embodiment calibrates a... | 06/22/2010 |
