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| Number | Title | Issue Date |
| 8443223 | Method and system for balancing receive-side supply load Described are digital communication systems that transmit and receive parallel sets of data symbols. Differences between successive sets of symbols induce changes in the current used to express the symbol sets, and thus introduce supply ripple. A receiver adds compe... | 05/14/2013 |
| 8442210 | Signal line routing to reduce crosstalk effects A signaling system is disclosed. The system includes a transmitter comprising an encoder to encode a data signal such that the encoded data signal has a balanced number of logical 1s and 0s. The system also includes a receiver having a decoder to decode the encoded ... | 05/14/2013 |
| 8441872 | Memory controller with adjustable width strobe interface A method of operation in a memory controller comprising generating a mode control signal to specify at least one of a first and second mode is disclosed. In the first mode, the memory controller is configured to operate by issuing a memory access command to initiate... | 05/14/2013 |
| 8432768 | Mesochronous signaling system with multiple power modes In a low-power signaling system, an integrated circuit device includes an open loop-clock distribution circuit and a transmit circuit that cooperate to enable high-speed transmission of information-bearing symbols unaccompanied by source-synchronous timing reference... | 04/30/2013 |
| 8432766 | Multi-column addressing mode memory system including an integrated circuit memory device A memory system includes a master device, such as a graphics controller or processor, and an integrated circuit memory device operable in a dual column addressing mode. The integrated circuit memory device includes an interface and column decoder to access a row of ... | 04/30/2013 |
| 8428210 | Apparatus and method for controlling a master/slave system via master device synchronization A method of operating a master/slave system includes the step of identifying a master receive data phase value to coordinate the transfer of data from a slave device without phase alignment circuitry to a master device with a universal phase aligner. Data is transfe... | 04/23/2013 |
| 8428196 | Equalizing receiver A signaling system is described. The signaling system comprises a transmit device, a receive device including a partial response receive circuit, and a signaling path coupling the transmit device and the receive device. The receive device observes an equalized signa... | 04/23/2013 |
| 8427891 | Hybrid volatile and non-volatile memory device with a shared interface circuit A composite, hybrid memory device including a first storage die having an array of volatile storage cells and a second storage die having an array of non-volatile storage cells disposed within an integrated circuit package. The hybrid memory device includes a shared... | 04/23/2013 |
| 8422590 | Apparatus and methods for differential signal receiving A differential signal receiver 106 implements intra-pair skew compensation for improving data transfer on a differential channel. In an embodiment, the receiver implements sampling by—multiple clocks with different phases such that the signals of the differ... | 04/16/2013 |
| 8422568 | Communication channel calibration for drift conditions A method and system provides for execution of calibration cycles from time to time during normal operation of the communication channel. A calibration cycle includes de-coupling the normal data source from the transmitter and supplying a calibration pattern in its p... | 04/16/2013 |
| 8415788 | System and method for dissipating heat from semiconductor devices A system includes a circuit board, a multi-die package, and a heat dissipator. The circuit board has substantially planar opposing first and second sides. The multi-die package includes a substrate and a first set of one or more semiconductor devices on a first subs... | 04/09/2013 |
| 8412906 | Memory apparatus supporting multiple width configurations Described are memory apparatus organized in memory subsections and including configurable routing to support multiple data-width configurations. Relatively narrow width configurations load fewer sense amplifiers, resulting in reduced power usage for relatively narro... | 04/02/2013 |
| 8407558 | Code-assisted error-detection technique Embodiments of a circuit are described. In this circuit, an encoder circuit encodes a set of N symbols as a given codeword in a code space, where the given codeword includes a set of M symbols. M drivers are coupled to the encoder circuit and are coupled to M links ... | 03/26/2013 |
| 8407441 | Method and apparatus for calibrating write timing in a memory system A system that calibrates timing relationships between signals involved in performing write operations is described. This system includes a memory controller which is coupled to a set of memory chips, wherein each memory chip includes a phase detector configured to c... | 03/26/2013 |
| 8405691 | Field sequential color encoding for displays The optical performance is enhanced of display systems that use field sequential color and pulse width modulation to generate color and color gray scale values. Such enhancement may be achieved by various data encoding methods disclosed herein that may include tempo... | 03/26/2013 |
| 8396109 | Adaptive receive-side equalization An adaptive receiver equalizes incoming data expressed as a series of symbols, the degree of equalization being adjusted by some adaptive control logic. An amplitude detector samples the amplitude of the eye openings of incoming symbols and conveys the resulting mea... | 03/12/2013 |
| 8395951 | Memory controller A memory component having a first and second interface. The first interface is provided to sample address information in response to a first clock signal. The first interface includes inputs to sample at least two bits of the address information in succession during... | 03/12/2013 |
| 8391338 | Methods for estimation and interference cancellation for signal processing A receiver in a CDMA system comprises a front end processor that generates a combined signal per source. A symbol estimator processes the combined signal to produce symbol estimates. An S-Matrix Generation module refines these symbol estimates based on the sub chann... | 03/05/2013 |
| 8391099 | Integrated circuit memory device, system and method having interleaved row and column control An integrated circuit memory device, system and method embodiments decode interleaved row and column request packets transferred on an interconnect at a first clock frequency. Separate row decode logic and column decode logic, clocked at a relatively slower second c... | 03/05/2013 |
| 8391039 | Memory module with termination component A module having first and second memory devices and a termination component. A first signal line is coupled to the first memory device to provide first data thereto, the first data to be stored in a memory array of the first memory device during a write operation. A... | 03/05/2013 |
| 8390546 | Line-at-a-time foil display A display device comprising a light guide (12), a front plate (14), and an intermediate electromechanically operable foil (16). Two electrode layers (22, 23) are arranged on either side of the foil (16) to induce electrostatic forc... | 03/05/2013 |
| 8385492 | Receiver circuit architectures Described are methods and circuits for margin testing digital receivers. These methods and circuits prevent margins from collapsing in response to erroneously received data, and can thus be used in receivers that employ historical data to reduce intersymbol interfer... | 02/26/2013 |
| 8384423 | Reference voltage and impedance calibration in a multi-mode interface A memory controller includes a transmit circuit coupled to an output node and a receive circuit coupled to an input node. The transmit circuit transmits first data to a memory device through the output node and the receive circuit is configured to receive second dat... | 02/26/2013 |
| 8380943 | Variable-width memory module and buffer A memory module having a plurality of memory devices and a memory buffer that translates between a variable width primary data port and a plurality of fixed width secondary data ports, each of which is coupled to one of the memory devices. The translation is effecte... | 02/19/2013 |
| 8380927 | Upgradable system with reconfigurable interconnect Described are systems that employ configurable on-die termination elements that allow users to select from two or more termination topologies. One topology is programmable to support rail-to-rail or half-supply termination. Another topology selectively includes fixe... | 02/19/2013 |
| 8380026 | Optical microstructures for light extraction and control The application of optical microstructures improve the quality of light available to the viewer of an optical display system, or any display which works on the concept of moving one surface into direct contact or close proximity of a light guide to extract light thr... | 02/19/2013 |
| 8379765 | Amplitude monitor for high-speed signals A serial communication system includes a receiver with an amplitude monitor. The amplitude monitor compares the input signal with a reference level in response to a sample clock. The sample clock is periodically phase shifted with respect to the incoming data so the... | 02/19/2013 |
| 8378699 | Self-test method for interface circuit An integrated circuit is described. The integrated circuit includes an interface circuit that includes a transmitter and a receiver. A generator in the integrated circuit is selectively coupled to the transmitter. The generator is to provide a test sequence that is ... | 02/19/2013 |
| 8378481 | Semiconductor module with micro-buffers The semiconductor module includes a plurality of memory die on a first side of a substrate and a plurality of buffer die on a second side of the substrate. Each of the memory die is disposed opposite and electrically coupled to one of the buffer die. ... | 02/19/2013 |
| RE44019 | Stacked semiconductor module The semiconductor module is provided that includes a semiconductor housing and a plurality of integrated circuit dice positioned within the housing. The semiconductor module also includes a programmable memory device positioned within the housing and electrically co... | 02/19/2013 |
| 8374558 | Antenna array with flexible interconnect for a mobile wireless device An antenna array can be mounted on a flexible substrate and connected by a flexible interconnect to an integrated circuit such as a radio frequency front end. The antenna array can be mounted in a device housing that includes radio frequency interference (RFI) shiel... | 02/12/2013 |
| 8374299 | Serial cancellation receiver design for a coded signal processing engine An interference cancelling receiver combines data from multiple paths after aligning to transmitter timing, and uses either an equalizer or a Rake receiver to compute symbol estimates. Interference estimates are generated from the symbol estimates, and multiple inte... | 02/12/2013 |
| 8370596 | Mechanism for enabling full data bus utilization without increasing data granularity A memory is disclosed comprising a first memory portion, a second memory portion, and an interface, wherein the memory portions are electrically isolated from each other and the interface is capable of receiving a row command and a column command in the time it take... | 02/05/2013 |
| 8369164 | Bimodal memory controller A memory controller has a communication path which is coupled to an external, wired electrical path. The memory controller includes at least two alternative interface circuits to communicate with the external, wired electrical path using signals having one of two di... | 02/05/2013 |
| 8365119 | Generating interface adjustment signals in a device-to-device interconnection system Described are a system and method to control interface timing and/or voltage operations of signals transmitted between devices. A processor may be coupled through one or more bus interfaces of a bus to one or more corresponding interface timing and/or voltage compar... | 01/29/2013 |
| 8365042 | Unidirectional error code transfer for both read and write data transmitted via bidirectional data link A controller includes a link interface that is to couple to a first link to communicate bi-directional data and a second link to transmit unidirectional error-detection information. An encoder is to dynamically add first error-detection information to at least a por... | 01/29/2013 |
| 8364937 | Executing misaligned load dependent instruction in second execution stage in parity protected mode in configurable pipelined processor A method includes providing a data processor having an instruction pipeline, where the instruction pipeline has a plurality of instruction pipeline stages, and where the plurality of instruction pipeline stages includes a first instruction pipeline stage and a secon... | 01/29/2013 |
| 8364926 | Memory module with reduced access granularity A memory module having reduced access granularity. The memory module includes a substrate having signal lines thereon that form a control path and first and second data paths, and further includes first and second memory devices coupled in common to the control path... | 01/29/2013 |
| 8364878 | Memory module having signal lines configured for sequential arrival of signals at a plurality of memory devices A memory module includes a substrate, a plurality of signal lines, a clock line and a plurality of memory devices. The plurality of signal lines including first and second signal lines routed alongside one another where, for each of the first and second signal lines... | 01/29/2013 |
| 8363493 | Memory controller having a write-timing calibration mode A memory controller outputs address bits and a first timing signal to a DRAM, each address bit being associated with an edge of the first timing signal and the first timing signal requiring a first propagation delay time to propagate to the DRAM. The memory controll... | 01/29/2013 |
