Quotables
"Flight by machines heavier than air is unpractical and insignificant, if not utterly impossible."
Simon Newcomb, astronomer ; Said in 1902, less than two years before the first flight at Kitty Hawk
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| Number | Title | Issue Date |
| 8145469 | System and method for providing compact mapping between dissimilar memory systems A memory mapping system for compactly mapping dissimilar memory systems and methods for manufacturing and using same. The mapping system maps a source memory system into a destination memory system by partitioning the source memory system and disposing memory conten... | 03/27/2012 |
| 7937258 | System and method for providing compact mapping between dissimilar memory systems A memory mapping system for providing compact mapping between dissimilar memory systems and methods for manufacturing and using same. The memory mapping system can compactly map contents from one or more first memory systems into a second memory system without a los... | 05/03/2011 |
| 7738398 | System and method for configuring communication systems An identification system for identifying and validating selected components of a communication system and methods for manufacturing and using same. The communication system includes a host system that is configured to couple with one or more target systems. When the... | 06/15/2010 |
| 7640155 | Extensible memory architecture and communication protocol for supporting multiple devices in low-bandwidth, asynchronous applications A target interface system for interfacing selected components of a communication system and methods for manufacturing and using same. The target interface system includes target interface logic that is distributed among a plurality of reconfigurable logic devices. B... | 12/29/2009 |
| 7606697 | System and method for resolving artifacts in differential signals A signal conversion system for interfacing selected components of a communication system and methods for manufacturing and using same. The signal conversion system converts selected logic signals from one system component into a pair of differential logic signals an... | 10/20/2009 |
| 7555424 | Method and apparatus for rewinding emulated memory circuits Methods and apparatus, including computer program products, for emulating a memory circuit in a logic emulation system. The system includes at least one log memory associated with the emulated memory. Each log memory location is marked invalid at a predetermined tim... | 06/30/2009 |
| 7555423 | Emulation processor interconnection architecture The present system and methods are directed to the interconnection of clusters of emulation processors comprising emulation processors in a software-driven hardware design verification system. The processors each output one NBO output signal. The clusters are interc... | 06/30/2009 |
| 7440884 | Memory rewind and reconstruction for hardware emulator A method and apparatus for debugging circuit designs having random access memory therein. The circuit design is emulated on a hardware logic emulator. The RAM emulated by the emulator can be rewound to a previous state, and then replayed. The RAM emulated by the emu... | 10/21/2008 |
| 7440866 | System and method for validating an input/output voltage of a target system A target interface system for interfacing selected components of a communication system and methods for manufacturing and using same. Being reconfigurable to support an extensive range of conventional input/output technologies, the target interface system downloads ... | 10/21/2008 |
| 7404160 | Method and system for hardware based reporting of assertion information for emulation and hardware acceleration A method and system for hardware based reporting of assertion information for emulation and hardware acceleration is disclosed. In one embodiment, a method of performing assertion-based verification, comprises providing a user interface to design assertions that aid... | 07/22/2008 |
| 7379861 | Dynamic programming of trigger conditions in hardware emulation systems An improved emulation system having an improved trigger mechanism is disclosed. During the compilation of the circuit design, a portion of the emulation resources are reserved for dynamic netlists. The dynamic netlists allows a user to create arbitrary trigger circu... | 05/27/2008 |
| 7356455 | Optimized interface for simulation and visualization data transfer between an emulation system and a simulator An optimized interface for simulation and visualization data transfer between an emulation system and simulator is disclosed. In one embodiment, a method of transferring data between a simulator to an emulator across an interface, comprises updating a simulator buff... | 04/08/2008 |
| 7260794 | Logic multiprocessor for FPGA implementation A design verification system utilizing programmable logic devices having varying numbers of logic processors, macro processors, memory processors and general purpose processors programmed therein is disclosed. These various processors can execute Boolean functions, ... | 08/21/2007 |
| 7257524 | Simulation and timing control for hardware accelerated simulation A fully synthesizeable Simulation Control Module (SCM) controls and monitors the simulation of a design under test (DUT). A clock generator within the SCM and a Software clock facility residing on the host workstation are responsible for providing the clocks for the... | 08/14/2007 |
| 7107203 | High speed software driven emulator comprised of a plurality of emulation processors with improved board-to-board interconnection cable length identification system A system and method for determining which of several possible cable lengths has been used by reversing the end-to-end correspondence of at least two conductors in the cable. A different two conductors are selected to identify respective different cable lengths. Each... | 09/12/2006 |
| 7089538 | High speed software driven emulator comprised of a plurality of emulation processors with a method to allow memory read/writes without interrupting the emulation A software driven emulator in which the stored emulation program for a processor module is compiled to include a code bit or bits in the emulation instruction step sequence that is decoded as main data memory disable command. Thus, once in each emulation program cyc... | 08/08/2006 |
| 7054802 | Hardware-assisted design verification system using a packet-based protocol logic synthesized for efficient data loading and unloading A system is provided to increase the accessibility of registers and memories in a user's design undergoing functional verification in a hardware-assisted design verification system. A packet-based protocol is used to perform data transfer operations between a host w... | 05/30/2006 |
| 7048560 | System and method for ejecting a high extraction force electromechanical connector A mechanism is described for effecting the ejection of a high extraction force electromechanical connector from its mate by utilizing an ejector mechanism and without requiring custom design or manufacturing of the mating connector. One embodiment achieves this by w... | 05/23/2006 |
| 7047179 | Clustered processors in an emulation engine Clusters of processors are interconnected as an emulation engine such that processors share input and data stacks, and the setup and storing of results are done in parallel, but the output of one evaluation unit is connected to the input of the next evaluation unit.... | 05/16/2006 |
| 7043417 | High speed software driven emulator comprised of a plurality of emulation processors with improved multiplexed data memory In an emulator processor cluster, the read ports of a shared input and data memory stack are time multiplexed to serve more than one processor. In an exemplary embodiment of the invention, a 256×8 memory array serves as the shared memory for four processors in a cl... | 05/09/2006 |
| 6901359 | High speed software driven emulator comprised of a plurality of emulation processors with a method to allow high speed bulk read/write operation synchronous DRAM while refreshing the memory A system and method for bulk transfer to and from the SRAMs in which a starting memory address is latched and is then incremented every clock cycle to generate a new memory address. The addresses are decoded and memory requests are pipelined to the SRAM memory, one ... | 05/31/2005 |
| 6850880 | High speed software driven emulator comprised of a plurality of emulation processors with an improved maintenance bus that streams data at high speed A software driven emulator has a maintenance bus operating protocol mode in which, after an initial address phase, data is streamed continuously by automatically incrementing the sending and receiving addresses. ... | 02/01/2005 |
| 6842729 | Apparatus for emulation of electronic systems A system for physical emulation of electronic circuits or systems includes a data entry workstation where a user may input data representing the circuit or system configuration. This data is converted to a form suitable for programming an array of programmable gate ... | 01/11/2005 |
| 6832185 | Non-synchronous hardware emulator A hardware emulator chip contains an array of cells and a programmable interconnection array. Each cell performs only a single logic function, which is configurable. The chips run asynchronously to one another, and within each chip cells are enabled by a sequential ... | 12/14/2004 |
| 6782355 | Apparatus for improving concurrent behavior modeling with emulation A hardware design emulation system that includes one or more emulators and one or more associated run-time assist units (RTAUs). The emulator logic is a combination of user model logic, reflecting the hardware design, and non-user model logic. A handshaking controll... | 08/24/2004 |
| 6732068 | Memory circuit for use in hardware emulation system A hardware emulation system is disclosed which reduces hardware cost by time-multiplexing multiple design signals onto physical logic chip pins and printed circuit board. The reconfigurable logic system of the present invention comprises a plurality of reprogrammabl... | 05/04/2004 |
| 6728667 | Multiple instantiation system This invention features a method of simultaneously conducting simulation testing of a plurality of simulated device designs using cycle-based software which is capable of simultaneously executing a number of simulation tests along separate test pathways for each sim... | 04/27/2004 |
