Assignee: Qimonda North America Corp.

Location: Cary, NC
No. of patents: 69

Number	Title	Issue Date
8138028	Method for manufacturing a phase change memory device with pillar bottom electrode A method for manufacturing a mushroom-cell type phase change memory is based upon manufacturing a pillar of bottom electrode material upon a substrate including an array of conductive contacts in electrical communication with access circuitry. A layer of electrode m...	03/20/2012
8124950	Concentric phase change memory element A memory device including a first electrode; a second electrode; and a memory cell positioned between the first electrode and the second electrode, the memory cell including a core of a first phase change material and a cladding of a second phase change material, wh...	02/28/2012
7932507	Current constricting phase change memory element structure A layer of nanoparticles having a dimension on the order of 10 nm is employed to form a current constricting layer or as a hardmask for forming a current constricting layer from an underlying insulator layer. The nanoparticles are preferably self-aligning and/or sel...	04/26/2011
7886122	Method and circuit for transmitting a memory clock signal Embodiments of the invention generally provide a method and apparatus for transmitting and receiving clock signals. In one embodiment, the method includes receiving, at a memory device, a first clock signal and a second clock signal. The frequency of the first clock...	02/08/2011
7872931	Integrated circuit with control circuit for performing retention test An integrated circuit includes an array of memory cells, a clock generator configured to generate a clock signal, and a control circuit configured to perform a retention test on the array of memory cells based on the clock signal. A period of the clock signal define...	01/18/2011
7863610	Integrated circuit including silicide region to inhibit parasitic currents An integrated circuit is disclosed. One embodiment includes a first diode, a second diode, and a semiconductor line coupled to the first diode and the second diode. The line includes a first silicide region between the first diode and the second diode. ...	01/04/2011
7822910	Method of flexible memory segment assignment using a single chip select Embodiments of the invention may generally provide techniques that allow mapping of memory devices in a multi-chip package (MCP) to memory segments of an address space. For some embodiments, a multi-bit device ID, which corresponds to a memory segment to which that ...	10/26/2010
7796424	Memory device having drift compensated read operation and associated method A memory includes a memory array and a read control circuit configured to effectuate a read operation of a memory cell in the array. The read control circuit is configured so that the read operation contemplates one or more drift conditions associated with the memor...	09/14/2010
7782703	Semiconductor memory having a bank with sub-banks Methods and apparatus that provide an additional level(s) of hierarchy within a bank of a Dynamic Random Access Memory (DRAM) are provided. The bank has a plurality of separately addressable sub-banks. ...	08/24/2010
7773438	Integrated circuit that stores first and second defective memory cell addresses An integrated circuit including an array of memory cells, volatile storage, non-volatile storage and a circuit. The circuit is configured to sense first addresses of first defective memory cells from the non-volatile storage to obtain sense first addresses. The circ...	08/10/2010
7760546	Integrated circuit including an electrode having an outer portion with greater resistivity An integrated circuit includes a first electrode including an inner portion and an outer portion laterally surrounding the inner portion. The outer portion has a greater resistivity than the inner portion. The integrated circuit includes a second electrode and resis...	07/20/2010
7746098	Termination switching based on data rate Embodiments of the invention are generally related to systems comprising devices connected by a bus. A device in the system may include termination control logic capable of detecting changes in the system clock frequency. Upon detecting a clock frequency, the termin...	06/29/2010
7745812	Integrated circuit including vertical diode An integrated circuit includes a vertical diode defined by crossed line lithography. ...	06/29/2010
7728638	Electronic system that adjusts DLL lock state acquisition time One embodiment provides an electronic system including a delay locked loop and a control circuit. The delay locked loop is configured to be enabled and update lock state data and to be disabled and store the locked state data. The control circuit is configured to pe...	06/01/2010
7721010	Method and apparatus for implementing memory enabled systems using master-slave architecture Embodiments of the invention generally provide a system, method, and memory device for accessing memory. In one embodiment, a first memory device includes command decoding logic configured to decode commands issued to the first memory device and a second memory devi...	05/18/2010
7719886	Multi-level resistive memory cell using different crystallization speeds An integrated circuit includes a first electrode and a second electrode. The integrated circuit includes a first resistivity changing material between the first electrode and the second electrode and a second resistivity changing material between the first electrode...	05/18/2010
7719244	Method and apparatus for enabling a voltage regulator A voltage regulator circuit is operated by enabling a bias network operable to set a bias current in an amplifier. A startup circuit is connected to the bias network, the startup circuit operable to assist the bias network in setting the amplifier bias current durin...	05/18/2010
7718464	Integrated circuit fabricated using an oxidized polysilicon mask An integrated circuit includes a first electrode, a second electrode, and dielectric material including an opening. The opening is defined by etching the dielectric material based on an oxidized polysilicon mask formed using a keyhole process. The integrated circuit...	05/18/2010
7715264	Method and apparatus for selectively disabling termination circuitry In one embodiment, an electronic device comprises control circuitry. The control circuitry disables termination circuitry coupled to one or more input/output (I/O) signals of the electronic device during at least a portion of a relatively low frequency operation whi...	05/11/2010
7714315	Thermal isolation of phase change memory cells A memory includes an array of resistive memory cells, bit lines between rows of the memory cells for accessing the memory cells, and a conductive plate coupled to each of the memory cells. ...	05/11/2010
7710754	Method of simple chip select for memory subsystems Embodiments of the invention may generally provide techniques that allow a single externally supplied chip select signal to be used to independently select a plurality of devices in a multi-chip package (MCP). For some embodiments, higher order address bits are comp...	05/04/2010
7694196	Self-diagnostic scheme for detecting errors The present invention is generally related to integrated circuit devices, and more particularly, to methods and systems of a multi-chip package (MCP) containing a self-diagnostic scheme for detecting errors in the MCP. The MCP generally comprises a controller, at le...	04/06/2010
7692949	Multi-bit resistive memory A memory includes a first multi-bit resistive memory cell and a single bit resistive memory cell. The single bit resistive memory cell is for storing a bit indicating whether data stored in the first multi-bit resistive memory cell is inverted. ...	04/06/2010
7688665	Structure to share internally generated voltages between chips in MCP Embodiments of the invention generally provide an apparatus and technique for sharing an internally generated voltage between devices of a multi-chip package (MCP). The internally generated voltage may be shared via a conductive structure that electrically couples t...	03/30/2010
7688618	Integrated circuit having memory having a step-like programming characteristic A memory cell includes a first electrode, a second electrode, and phase-change material between the first electrode and the second electrode. The phase-change material has a step-like programming characteristic. ...	03/30/2010
7684273	Sense amplifier biasing method and apparatus A memory device includes sense amplifier circuitry, a current sink and a resistive element. The sense amplifier circuitry is operable to evaluate data read from a memory array included in the memory device responsive to a bias voltage applied to the sense amplifier ...	03/23/2010
7679980	Resistive memory including selective refresh operation A memory includes an array of phase change memory cells and a first circuit. The first circuit is for refreshing only memory cells within the array of phase change memory cells that are programmed to non-crystalline states in response to a request for a refresh oper...	03/16/2010
7679074	Integrated circuit having multilayer electrode An integrated circuit includes a contact and a first electrode coupled to the contact. The first electrode includes at least two electrode material layers. The at least two electrode material layers include different materials. The integrated circuit includes a seco...	03/16/2010
7671353	Integrated circuit having contact including material between sidewalls An integrated circuit includes a bottom electrode, a top electrode, resistivity changing material between the bottom electrode and the top electrode, and a contact contacting the top electrode. The contact includes a bottom and sidewalls. The integrated circuit incl...	03/02/2010
7663955	Delayed sense amplifier multiplexer isolation Methods and circuit arrangements are provided for improving equalization of sense nodes of a sense amplifier in a semiconductor memory device. When a memory array segment on a side a sense amplifier has a bitline leakage anomaly for which the sense amplifier is to b...	02/16/2010
7663909	Integrated circuit having a phase change memory cell including a narrow active region width A memory cell includes a first electrode and an opposing second electrode, and a memory stack between the first and second electrodes. The memory stack includes a first layer of thermal isolation material contacting the first electrode, a second layer of thermal iso...	02/16/2010
7652914	Memory including two access devices per phase change element A memory includes a bit line and a phase change element. A first side of the phase change element is coupled to the bit line. The memory includes a first access device coupled to a second side of the phase change element and a second access device coupled to the sec...	01/26/2010
7639066	Circuit and method for suppressing gate induced drain leakage An electrical circuit comprising a first metal oxide silicon (MOS) n type field effect transistor (NFET) or p type field effect transistor (PFET) and a second MOS NFET or PFET of the same conductivity type as the first NFET or PFET, wherein the drain of the first NF...	12/29/2009
7636250	Random access memory that selectively provides data to amplifiers A random access memory including a first amplifier, a second amplifier, a first data path, a second data path, and a first circuit. The first data path receives first data via first memory cells and the second data path receives second data via second memory cells. ...	12/22/2009
7626858	Integrated circuit having a precharging circuit A memory includes a phase change element having a first side and a second side and a first line coupled to the first side of the element. The memory includes an access device coupled to the second side of the element and a second line coupled to the access device fo...	12/01/2009
7623401	Semiconductor device including multi-bit memory cells and a temperature budget sensor One embodiment provides a semiconductor device including a plurality of multi-bit memory cells, a first temperature budget sensor, and a circuit. Each of the plurality of multi-bit memory cells is programmable into each of more than two states. The circuit compares ...	11/24/2009
7619936	System that prevents reduction in data retention One embodiment of the present invention provides a system including a tester and a back end manufacturing system. The tester tests a resistive memory and obtains configuration data for the resistive memory. The back end manufacturing system prevents temperatures in ...	11/17/2009
7619917	Memory cell with trigger element A memory device includes a plurality of word lines extending as rows and bit lines extending as columns. A memory cell is coupled between a word line and a bit line, wherein the memory cell includes a unipolar memory element selectively coupled to the bit line via a...	11/17/2009
7617354	Abbreviated burst data transfers for semiconductor memory An integrated circuit having a nominal minimum burst length defined by a nominal data prefetch size transfers data by accepting an abbreviated burst data read request directed to a first bank, prefetching less than the nominal data prefetch size, and providing the d...	11/10/2009
7611972	Semiconductor devices and methods of manufacture thereof Semiconductor devices and methods of manufacture thereof are disclosed. A preferred embodiment comprises a method of forming an insulating material layer. The method includes forming a barrier layer and forming a rare earth element-containing material layer over the...	11/03/2009

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Assignee: Qimonda North America Corp.