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| Number | Title | Issue Date |
| 8103978 | Method for establishing scattering bar rule A method for establishing a scattering bar rule for a mask pattern for fabricating a device is provided. The method is described as follows. First, at least one image simulation model is established according to the mask pattern and a process reference set used for ... | 01/24/2012 |
| 8071970 | Phase change memory device and fabrication method thereof A phase change memory device comprising an electrode, a phase change layer crossing and contacting the electrode at a cross region thereof, and a transistor comprising a source and a drain, wherein the drain of the transistor electrically connects the electrode or t... | 12/06/2011 |
| 7989795 | Phase change memory device and method for fabricating the same A phase change memory device is provided. The phase change memory device comprises a substrate. An electrode layer is on the substrate. A phase change memory structure is on the electrode layer and electrically connected to the electrode layer, wherein the phase cha... | 08/02/2011 |
| 7932565 | Integrated circuit structure having bottle-shaped isolation An integrated circuit structure comprises a semiconductor substrate, a device region positioned in the semiconductor substrate, an insulating region adjacent to the device region, an isolation structure positioned in the insulating region and including a bottle port... | 04/26/2011 |
| 7919384 | Method of making planar-type bottom electrode for semiconductor device A method of making planar-type bottom electrode for semiconductor device is disclosed. A sacrificial layer structure is formed on a substrate. Multiple first trenches are defined in the sacrificial layer structure, wherein those first trenches are arranged in a firs... | 04/05/2011 |
| 7872307 | Power MOSFET array A power metal-oxide-semiconductor field-effect transistor (MOSFET) array structure is provided. The power MOSFET array is disposed under a gate pad, and space under the gate pad can be well used to increase device integration. When the array and the conventional pow... | 01/18/2011 |
| 7871884 | Manufacturing method of dynamic random access memory A method for manufacturing the DRAM includes first providing a substrate where patterned first mask layer and deep trenches exposed by the patterned first mask layer are formed. Deep trench capacitors are formed in the deep trenches and each of the deep trench capac... | 01/18/2011 |
| 7851253 | Phase change memory device and fabricating method A phase change memory device is provided. The phase change memory device includes a substrate with a first electrode layer formed thereon. A first phase change memory structure is on the first electrode layer and electrically connected to the first electrode layer. ... | 12/14/2010 |
| 7808019 | Gate structure A gate structure includes a substrate, a gate dielectric layer, a first conductive layer, a second conductive layer, a cap layer and a first insulating spacer. The gate dielectric layer is disposed on the substrate. The first conductive layer is disposed on the gate... | 10/05/2010 |
| 7781830 | Recessed channel transistor and method for preparing the same A recessed channel transistor comprises a semiconductor substrate having a trench isolation structure, a gate structure having a lower block in the semiconductor substrate and an upper block on the semiconductor substrate, two doped regions positioned at two sides o... | 08/24/2010 |
| 7781303 | Method for preparing a shallow trench isolation A method for preparing a shallow trench isolation comprising the steps of forming at least one trench in a semiconductor substrate, performing an implanting process to implant nitrogen-containing dopants into an upper sidewall of the trench such that the concentrati... | 08/24/2010 |
| 7764555 | Leakage testing method for dynamic random access memory having a recess gate A leakage testing method for a DRAM having a recess gate is provided. The method includes the steps of: programming to set the first storage unit and the second storage unit of a same memory cell with different storage statuses; and disturbing one of the word lines ... | 07/27/2010 |
| 7759252 | Method of two-step backside etching The present invention is related to a method of two-step backside-etching. First, a substrate with a plurality of hard masks is provided. Next, the back and the edge of the substrate are backside-etched to remove parts of the hard masks on the back and the edge of t... | 07/20/2010 |
| 7732801 | Phase change memory device A phase change memory device is provided. The phase change memory device includes a substrate with a first electrode layer formed thereon. A first phase change memory structure is on the first electrode layer and electrically connected to the first electrode layer. ... | 06/08/2010 |
| 7729183 | Data sensing method for dynamic random access memory A data sensing method for a dynamic random access memory including a storage capacitor configured to store data, a bit line, a transistor connecting the storage capacitor and the bit line, a reference bit line, and a sense amplifier connecting the bit line and the r... | 06/01/2010 |
| 7679163 | Phase-change memory element A phase-change memory element for reducing heat loss is disclosed. The phase-change memory element comprises a composite layer, wherein the composite layer comprises a dielectric material and a low thermal conductivity material. A via hole is formed within the compo... | 03/16/2010 |
| 7679075 | Phase change memory array and fabrication thereof A phase change memory array is disclosed, comprising a first cell having a patterned phase change layer, and a second cell having a patterned phase change layer, wherein the patterned phase change layer of the first cell and the patterned phase change layer of the s... | 03/16/2010 |
| 7678606 | Phase change memory device and fabrication method thereof A phase change memory device is disclosed. A second conductive spacer is under a first conductive spacer. A phase change layer comprises a first portion substantially parallel to the first and second conductive spacers and a second portion on top of the second condu... | 03/16/2010 |
| 7675054 | Phase change memory devices and methods for fabricating the same Phase change memory devices and methods for fabricating the same are provided. A phase change memory device includes a first conductive electrode disposed in a first dielectric layer. A second dielectric layer is disposed over the first dielectric layer. A phase cha... | 03/09/2010 |
| 7672176 | Writing circuit for a phase change memory A writing circuit for a phase change memory is provided. The writing circuit comprises a driving current generating circuit, a first switch device, a first memory cell and a second switch device. The driving current generating circuit provides a writing current to t... | 03/02/2010 |
| 7670869 | Semiconductor device and fabrications thereof A memory device is disclosed. A pillar structure comprises a first electrode layer, a dielectric layer overlying the first electrode layer, and a second electrode layer overlying the dielectric layer. A phase change layer covers a surrounding of the pillar structure... | 03/02/2010 |
| 7660147 | Programming method for phase change memory A programming method for a phase change memory based on the phase transformations between amorphous and crystalline phases is disclosed. The programming method comprises a current pulse with step waveform providing a first crystallization current pulse to the phase ... | 02/09/2010 |
| 7635626 | Method of manufacturing dynamic random access memory A method of manufacturing a DRAM includes firstly providing a substrate. Many transistors are then formed on the substrate. Next, a first and a second LPCs are formed between the transistors. A first dielectric layer is then formed on the substrate, and a first open... | 12/22/2009 |
| 7622352 | Multi-step gate structure and method for preparing the same A multi-step gate structure comprises a semiconductor substrate having a multi-step structure, a gate oxide layer positioned on the multi-step structure and a conductive layer positioned on the gate oxide layer. Preferably, the gate oxide layer has different thickne... | 11/24/2009 |
| 7595467 | Fault detection system and method for managing the same A fault detection system comprises a data server configured to collect parameters incoming from at least one apparatus, at least one fault-sensing module configured to generate an alarm signal if the parameter exceeds a predetermined specification, a monitoring modu... | 09/29/2009 |
| 7592219 | Method of fabricating capacitor over bit line and bottom electrode thereof A method of fabricating a capacitor over bit line (COB) is provided. First, a substrate is provided and a plurality of word lines is formed on the substrate. Next, a plurality of landing plug contacts (LPCs) are formed between the word lines and a plurality of first... | 09/22/2009 |
| 7582524 | Method for preparing a memory structure A method for preparing a memory structure comprises the steps of forming a plurality of line-shaped blocks on a dielectric structure of a substrate, and forming a first etching mask exposing a sidewall of the line-shaped blocks. A portion of the line-shaped blocks i... | 09/01/2009 |
| 7569909 | Phase change memory devices and methods for manufacturing the same Phase change memory devices and methods for manufacturing the same are provided. An exemplary embodiment of a phase change memory device comprises a substrate. A dielectric layer is formed over the substrate and a phase change material layer is embedded in the diele... | 08/04/2009 |
| 7569845 | Phase-change memory and fabrication method thereof A phase-change memory comprises a bottom electrode formed on a substrate. A first isolation layer is formed on the bottom electrode. A top electrode is formed on the isolation layer. A first phase-change material is formed in the first isolation layer, wherein the t... | 08/04/2009 |
| 7569460 | Capacitor structure and method for preparing the same A capacitor structure comprises a substrate having a contact plug, a conductive cylinder positioned on the substrate and an electroplating structure covering the conductive cylinder, wherein a bottom electrode of the capacitor structure comprises the conductive cyli... | 08/04/2009 |
| 7566895 | Phase change memory device and method for fabricating the same A phase change memory device is provided. The phase change memory device includes a substrate comprising a stacked structure. The stacked structure comprises a plurality of insulating layers and conductive layers. Any two of the conductive layers are spaced apart by... | 07/28/2009 |
| 7557407 | Recessed gate structure and method for preparing the same A recessed gate structure comprises a semiconductor substrate, a recess positioned in the semiconductor substrate, a gate oxide layer positioned in the recess and a conductive layer positioned on the gate oxide layer, wherein the semiconductor substrate has a multi-... | 07/07/2009 |
| 7541116 | Mask at frequency domain and method for preparing the same and exposing system using the same A mask at frequency domain comprises a plurality of amplitude patterns positioned on a first surface of the mask and a plurality of phase patterns positioned on a second surface of the mask. The amplitude patterns have different vertical thicknesses to change the am... | 06/02/2009 |
| 7538043 | Phase change memory device and fabrication method thereof A phase change memory device comprising an electrode, a phase change layer crossing and contacting the electrode at a cross region thereof, and a transistor comprising a source and a drain, wherein the drain of the transistor electrically connects the electrode or t... | 05/26/2009 |
| 7538018 | Gate structure and method for fabricating the same, and method for fabricating memory and CMOS transistor layout A method for fabricating a gate structure is provided. A pad oxide layer, a pad conductive layer and a dielectric layer are sequentially formed over a substrate. A portion of the dielectric layer is removed to form an opening exposing a portion of the pad conductive... | 05/26/2009 |
| 7535050 | Memory structure with high coupling ratio A memory structure comprising a plurality of memory cells is described. Each memory cell comprises a substrate, a shallow trench isolation, a spacer, a tunnel oxide, and a floating gate. The shallow trench isolation in the substrate is used to define an active area.... | 05/19/2009 |
| 7531438 | Method of fabricating a recess channel transistor A method of fabricating a recess channel transistor is provided. First, a hard mask is formed on a doped-semiconductor layer and a substrate. The doped-semiconductor layer and the substrate are etched to form a trench and define a source/drain in the doped-semicondu... | 05/12/2009 |
| 7524732 | Semiconductor device with L-shaped spacer and method of manufacturing the same A semiconductor device with an L-shape spacer and the method for manufacturing the same are provided. The semiconductor device comprises a substrate, a composite spacer, and a tunnel insulating layer. The substrate comprises a shallow trench isolation structure and ... | 04/28/2009 |
| 7521372 | Method of fabrication of phase-change memory A phase-change memory and fabrication method thereof. The phase-change memory comprises a transistor, and a phase-change material layer. In particular, the phase-change material layer is directly in contact with one electrical terminal of the transistor. Particularl... | 04/21/2009 |
| 7510955 | Method of fabricating multi-fin field effect transistor A multi-fin field effect transistor includes a substrate, an oxide layer, a conductive layer, a gate oxide layer, and a doped region is provided. The substrate is surrounded by a trench, and there are at least two fin-type silicon layers formed in the substrate in a... | 03/31/2009 |
