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| Number | Title | Issue Date |
| 7584320 | Sliced crossbar architecture with no inter-slice communication A memory crossbar adapted to transmit a memory transaction to a network resource. The memory crossbar includes a plurality of input ports. Each of the plurality of input ports includes a TAGS generator and a queue adapted to receive a first portion of a first memory... | 09/01/2009 |
| 7565475 | Layered crossbar for interconnection of multiple processors and shared memories Apparatus and methods are disclosed for processing memory transaction requests and memory transaction results between multiple processors and multiple shared memories, where the communications path between the multiple processors and shared memories is provided by a... | 07/21/2009 |
| 7426603 | Memory bus arbitration using memory bank readiness A method, apparatus, and computer program product includes identifying a plurality of memory transactions to be sent over a memory bus to a memory having a plurality of memory banks, each memory transaction addressed to one of the memory banks, the memory bus incapa... | 09/16/2008 |
| 7275126 | Sliced crossbar architecture with no inter-slice communication A memory crossbar adapted to transmit a memory transaction to a network resource. The memory crossbar includes a plurality of input ports. Each of the plurality of input ports includes a TAGS generator and a queue adapted to receive a first portion of a first memory... | 09/25/2007 |
| 7275112 | Efficient serialization of bursty out-of-order results A method, apparatus, and computer program product includes serially receiving, from a source, a plurality of forward messages each addressed to one of a plurality of destinations; receiving a plurality of availability signals, each availability signal indicating tha... | 09/25/2007 |
| 7266616 | Method and system for digital rendering over a network Digital rendering over a network is described. Rendering resources associated with a project are stored in a project resource pool at a rendering service site, and for each rendering request received from a client site the project resource pool is compared to curren... | 09/04/2007 |
| 7234018 | Layered crossbar for interconnection of multiple processors and shared memories A method and apparatus includes a plurality of processor groups each having a plurality of processor switch chips each having a plurality of processors and a processor crossbar, each processor connected to the processor crossbar; a plurality of switch groups each ha... | 06/19/2007 |
| 7003539 | Efficiently determining a floor for a floating-point number An apparatus, method and computer program product for processing a binary floating-point number having a sign bit and a mantissa having a fraction portion. It includes identifying the fraction portion of the binary floating-point number; and replacing each bit of th... | 02/21/2006 |
| 6970454 | Sliced crossbar architecture with inter-slice communication A method and apparatus includes identifying an address portion of a first message in an address slice of a switch, the first message associated with a first priority, the address portion of the first message including a first routing portion specifying a network res... | 11/29/2005 |
| 6963896 | Method and system to implement an improved floating point adder with integrated adding and rounding Systems and methods to implement an improved floating point adder are presented. The adder integrates adding and rounding. According to an exemplary method, of adding two floating point numbers together, a first mantissa, a second mantissa, and an input bit are adde... | 11/08/2005 |
| 6961803 | Sliced crossbar architecture with no inter-slice communication A method and apparatus includes identifying a first portion of a first message in a first slice of a switch, the first message associated with a first priority, the first portion of the first message including a first routing portion specifying a network resource; i... | 11/01/2005 |
| 6836815 | Layered crossbar for interconnection of multiple processors and shared memories A method and apparatus includes a plurality of processor groups each having a plurality of processor switch chips each having a plurality of processors and a processor crossbar, each processor connected to the processor crossbar; a plurality of switch groups each ha... | 12/28/2004 |
