Assignee: P.A. Semi, Inc.

Location: Santa Clara, CA
No. of patents: 25

Number	Title	Issue Date
7529866	Retry mechanism in cache coherent communication among agents An interface unit may comprise a buffer configured to store requests that are to be transmitted on an interconnect and a control unit coupled to the buffer. In one embodiment, the control unit is coupled to receive a retry response from the interconnect during a res...	05/05/2009
7500044	Digital phase relationship lock loop In one embodiment, an apparatus comprises a first clocked storage device operable in a first clock domain corresponding to a first clock signal. The first clocked storage device has an input coupled to receive one or more bits transmitted on the input from a second ...	03/03/2009
7496695	Unified DMA In one embodiment, an apparatus comprises a first interface circuit, a direct memory access (DMA) controller coupled to the first interface circuit, and a host coupled to the DMA controller. The first interface circuit is configured to communicate on an interface ac...	02/24/2009
7493451	Prefetch unit In one embodiment, a processor comprises a prefetch unit coupled to a data cache. The prefetch unit is configured to concurrently maintain a plurality of separate, active prefetch streams. Each prefetch stream is either software initiated via execution by the proces...	02/17/2009
7474571	Integrated circuit with separate supply voltage for memory that is different from logic circuit supply voltage In one embodiment, an integrated circuit comprises at least one logic circuit supplied by a first supply voltage and at least one memory circuit coupled to the logic circuit and supplied by a second supply voltage. The memory circuit is configured to be read and wri...	01/06/2009
7472260	Early retirement of store operation past exception reporting pipeline stage in strongly ordered processor with load/store queue entry retained until completion In one embodiment, a processor comprises a retire unit and a load/store unit coupled thereto. The retire unit is configured to retire a first store memory operation responsive to the first store memory operation having been processed at least to a pipeline stage at ...	12/30/2008
7461190	Non-blocking address switch with shallow per agent queues In one embodiment, a switch is configured to be coupled to an interconnect. The switch comprises a plurality of storage locations and an arbiter control circuit coupled to the plurality of storage locations. The plurality of storage locations are configured to store...	12/02/2008
7454674	Digital jitter detector In one embodiment, a jitter detector comprises a logic circuit coupled to receive a plurality of inputs indicative of states captured from a plurality of outputs of a delay chain responsive to a first clock input and a plurality of clocked storage devices coupled to...	11/18/2008
7426601	Segmented interconnect for connecting multiple agents in a system In various embodiments, an apparatus comprises a plurality of agents and an interconnect. In one embodiment, the plurality of agents includes first through fourth agents. The interconnect comprises a plurality of segments that are switchable (e.g. using a plurality ...	09/16/2008
7412555	Ordering rule and fairness implementation In one embodiment, a controller comprises one or more transaction queues, one or more age counter circuits, and a control circuit. The transaction queues are configured to store a plurality of transaction requests, each having a transaction type. The age counter cir...	08/12/2008
7411409	Digital leakage detector that detects transistor leakage current in an integrated circuit In one embodiment, an integrated circuit includes at least one digital leakage detector that includes digital circuitry configured to detect an approximation of a magnitude of the leakage current in transistors of the integrated circuit and configured to generate a ...	08/12/2008
7398361	Combined buffer for snoop, store merging, load miss, and writeback operations In one embodiment, an interface unit comprises an address buffer and a control unit coupled to the address buffer. The address buffer is configured to store addresses of processor core requests generated by a processor core and addresses of snoop requests received f...	07/08/2008
7376817	Partial load/store forward prediction In one embodiment, a processor comprises a prediction circuit and another circuit coupled to the prediction circuit. The prediction circuit is configured to predict whether or not a first load instruction will experience a partial store to load forward (PSTLF) event...	05/20/2008
7373569	Pulsed flop with scan circuitry In one embodiment, a storage circuit comprises a first passgate having an input coupled to receive a signal representing a data input to the storage circuit and further having an output connected to a storage node in the storage circuit. The storage circuit also com...	05/13/2008
7373486	Partially decoded register renamer In one embodiment, a renamer comprises a plurality of storage locations and compare circuitry. Each storage location is assigned to a respective renameable resource and is configured to store an identifier corresponding to a youngest instruction operation that write...	05/13/2008
7372323	Resonance limiter circuits for an integrated circuit In one embodiment, an integrated circuit comprises resonance limiter circuits coupled to a power supply connection of the integrated circuit. The resonance limiter circuits are configured to detect oscillation on the power supply connection at a resonant frequency, ...	05/13/2008
7355905	Integrated circuit with separate supply voltage for memory that is different from logic circuit supply voltage In one embodiment, an integrated circuit comprises at least one logic circuit supplied by a first supply voltage and at least one memory circuit coupled to the logic circuit and supplied by a second supply voltage. The memory circuit is configured to be read and wri...	04/08/2008
7319344	Pulsed flop with embedded logic In one embodiment, an apparatus comprises a logic circuit, a plurality of passgates, at least one pulse generator, and a plurality of latch elements. The logic circuit has a plurality of inputs, and each of the passgates has an output directly connected to one of th...	01/15/2008
7277353	Register file In one embodiment, a memory circuit comprises one or more first memory cells, each of the one or more first memory cells configured to store at least one bit; one or more second memory cells, each of the one or more second memory cells configured to store at least o...	10/02/2007
7276925	Operating an integrated circuit at a minimum supply voltage In one embodiment, an integrated circuit comprises at least one measurement unit configured to generate an output indicative of a supply voltage at which the integrated circuit is operable for a given operating frequency and a control unit coupled to receive the out...	10/02/2007
7269682	Segmented interconnect for connecting multiple agents in a system In various embodiments, an apparatus comprises a plurality of agents and an interconnect. In one embodiment, the plurality of agents includes first through fourth agents. The interconnect comprises a plurality of segments that are switchable (e.g. using a plurality ...	09/11/2007
7268633	Voltage-controlled oscillator for low-voltage, wide frequency range operation In one embodiment, an apparatus comprises a voltage-controlled oscillator (VCO) that comprises a circuit coupled to receive an input control voltage to the VCO and configured to generate a second voltage responsive to the input control voltage, a summator coupled to...	09/11/2007
7245150	Combined multiplex or/flop In one embodiment, a combined mux/storage circuit comprises a latch element, a plurality of passgates connected to the latch element, and logic circuitry. Each passgate has an input coupled to receive a signal representing a respective mux input and is configured to...	07/17/2007
7218562	Recovering bit lines in a memory array after stopped clock operation In one embodiment, an apparatus comprises a plurality of memory cells; first and second bit lines coupled to the plurality of memory cells; a first and second bit line precharge circuits coupled to the first and second bit lines; and a control circuit coupled to the...	05/15/2007
7187606	Read port circuit for register file In one embodiment, a read port circuit includes a precharge circuit configured to precharge a first node in the read port circuit and a pulldown circuit coupled to the first node. The pulldown circuit is configured to conditionally discharge the first node responsiv...	03/06/2007

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Assignee: P.A. Semi, Inc.