Assignee: PMC-Sierra, Inc.

Location: Santa Clara, CA
No. of patents: 100

Number	Title	Issue Date
8116409	Method and apparatus for SerDes jitter tolerance improvement Apparatus and methods detect the presence of an isolated pulse in a communications signal, such as a data signal carrying data for a serializer/deserializer (SerDes). An example of an isolated pulse is a “1” pulse preceded and followed by “0” pulses, or a �...	02/14/2012
8023588	Adaptive predistortion of non-linear amplifiers with burst data Apparatus and methods control predistortion of an RF transmitter. A base station or a mobile station can utilize predistortion to improve linearity characteristics of the RF power amplifier. When used effectively, predistortion limits spectral growth such that the a...	09/20/2011
8020077	Forward error correction with self-synchronous scramblers Systems and methods correct multiplied errors generated by feedback taps in self-synchronous descramblers. The multiplication of errors degrades the performance of most linear cyclic error check codes. Disclosed techniques are general applicable to multiplied errors...	09/13/2011
8019029	Interference erasure using soft decision weighting of the Viterbi decoder input in OFDM systems Disclosed is a technique for mitigating the effect of an in-band interferer in Orthogonal Frequency Division Multiplexing (OFDM) wireless or wired networks that employ soft decision Viterbi decoder in the physical layer. The technique uses an independent estimation ...	09/13/2011
8019028	Run-length based spectral analysis Apparatus and methods determine a frequency associated with a relatively strong interfering signal (interferer) using relatively simple run-length counting techniques. Counts of run-lengths can be analyzed to estimate a frequency of the interferer. For example, a pe...	09/13/2011
8018251	Input/output interfacing with low power Apparatus and methods efficiently provide compatibility between CMOS integrated circuits and voltage levels that are different from that typically used by modern integrated circuits. For example, backwards compatibility can be desirable. Older signaling interfaces o...	09/13/2011
8004330	Reduction of electromagnetic interference for differential signals Apparatus and methods modulate the slew rate of high-speed edges of a differential digital signal. High-speed digital signals carried over printed circuit boards, backplanes, cables, and the like can radiate electromagnetic waves. These electromagnetic waves can cau...	08/23/2011
7986190	Jitter attenuation with a fractional-N clock synthesizer A circuit, such as, but not limited to, a digital phase-locked loop (PLL) or a transport timing loop, uses a fractional-N modulator and a fractional-N clock synthesizer to generate a clock signal, such as a transmit clock signal, from a reference clock signal. One e...	07/26/2011
7985644	Methods for forming fully segmented salicide ballasting (FSSB) in the source and/or drain region Transistor structures for relatively even current balancing within a device and methods for fabricating the same are disclosed. These devices can be used in relatively compact MOSFET Electrostatic Discharge (ESD) protection structures, such as in snapback devices. O...	07/26/2011
7982651	Power optimized ADC for wireless transceivers An analog-to-digital converter (ADC) of a radio receiver can consume a relatively large amount of power. It is typically desirable to minimize power consumption, particularly with battery-powered devices, such as in wireless receivers. In certain conditions, the eff...	07/19/2011
7979041	Out-of-channel received signal strength indication (RSSI) for RF front end The signal strength of an out-of-channel interferer is estimated by measuring the transition density of the sign of the down-converted signal. RF interferers at a higher or lower frequency than the desired RF signal appear as high frequency content in the down-conve...	07/12/2011
7969195	Active biasing in metal oxide semiconductor (MOS) differential pairs Apparatus and methods advantageously maintain transistors of open-drain differential pairs biased in the saturation region when “active,” rather in than the triode or linear region. The biasing techniques are effective over a broad range of process, voltage, and...	06/28/2011
7940088	High speed phase frequency detector Apparatus and methods detect missing clock edges. An improved phase frequency detector (PFD) can be used in, for example, a phase locked loop (PLL) or a delay locked loop (DLL). Conventional PFDs can miss clock edges. Disclosed is a missing clock edge detection circ...	05/10/2011
7936835	Adaptive signal decompression The adverse effects of RF and baseband circuits are mitigated using a post-compensation method wherein a transfer function that would un-distort or complement a distorted waveform is parameterized to a relatively small number of degrees of freedom; and the parameter...	05/03/2011
7916671	Echo cancellation for duplex radios In a Frequency Duplex Division (FDD) radio, the transmit and receive signals are separated by frequency. In a wireless application, the power of the transmitted signal is typically much larger than the power of the received signal. A duplexer is used to separate the...	03/29/2011
7913151	Forward error correction with self-synchronous scramblers Systems and methods correct multiplied errors generated by feedback taps in self-synchronous descramblers. The multiplication of errors degrades the performance of most linear cyclic error check codes. Disclosed techniques are general applicable to multiplied errors...	03/22/2011
7912151	Post-distortion filter for reducing sensitivity to receiver nonlinearities Methods and apparatus for reducing sensitivity to nonlinearities in the receiver of a digital communications system are disclosed. One aspect can be referred to as a Post-Distortion Decision Feedback Equalizer (PDFE). A gain stage is often implemented as a variable ...	03/22/2011
7904033	Constant gain digital predistortion controller for linearization of non-linear amplifiers The invention is related to methods and apparatus for controlling and adapting a digital predistortion linearizer for amplification of bandlimited signals using non-linear amplifiers. The control method advantageously permits the predistortion function applied by a ...	03/08/2011
7898295	Hot-pluggable differential signaling driver Apparatus and methods provide low voltage differential signaling (LVDS) driver with replica circuit biasing and protection for hot plugging. The replica biasing is non-intrusive in nature, and can control the voltage swing tightly over parametric variations. The abs...	03/01/2011
7777248	Semiconductor device for latch-up prevention A semiconductor device is provided for preventing Latch-up in Silicon Controlled Rectifiers (SCRs) when these SCRs become activated. Embodiments of the invention use a natively doped region having high resistance to separate the NPN transistor from the PNP transisto...	08/17/2010
7774424	Method of rate snooping in a SAS/SATA environment A method and apparatus for determining a set of common link rates for communication between two storage network elements in a storage network system. During the speed negotiation process, a controlling storage network element receives supported link rate information...	08/10/2010
7760122	Power optimized ADC for wireless transceivers An analog-to-digital converter (ADC) of a radio receiver can consume a relatively large amount of power. It is typically desirable to minimize power consumption, particularly with battery-powered devices, such as in wireless receivers. In certain conditions, the eff...	07/20/2010
7756197	Built in self test (BIST) for high-speed serial transceivers A relatively high-speed serial data transmitter incorporates built in self test (BIST). The BIST circuit advantageously provides tests modes to obviate the need to build expensive test equipment for high-speed serial data devices, such as a serializer/deserializer (...	07/13/2010
7743191	On-chip shared memory based device architecture A method and architecture are provided for SOC (System on a Chip) devices for RAID processing, which is commonly referred as RAID-on-a-Chip (ROC). The architecture utilizes a shared memory structure as interconnect mechanism among hardware components, CPUs and softw...	06/22/2010
7738617	Clock and data recovery locking technique for large frequency offsets Techniques and apparatus for a clock and data recovery circuit to lock to data having frequency offsets relative to a local clock reference are disclosed. One embodiment includes a multi-step frequency tracking system in which each step is used to track a sub-range ...	06/15/2010
7724781	Receive virtual concatenation processor A receive virtual concatenation processor (processor) is adapted to receive time-slot interleaved data carried over SONET/SDH frames. The processor first generates per time-slot data and subsequently generates per channel data. The processor supports virtual concate...	05/25/2010
7719806	Systems and methods for ESD protection A negative electrostatic discharge (ESD) protection network or circuit is described. The circuit can provide protection against a negative-going ESD transient. One embodiment, along with standard positive ESD protection networks, can discharge ESD currents in both p...	05/18/2010
7714643	Tuning of analog filters Apparatus and methods tune analog filters that are parts of systems. When an analog filter is inserted into a system, the analog filter can be difficult to tune because of the difficulty in observing the analog filter's characteristics without being interfered by ot...	05/11/2010
7679448	Continuous wave based bias method and apparatus for minimizing MOS transistor distortion A biasing circuit and method for minimizing distortion in a MOS transistor. A first CW source provides a first CW signal at the input of a replica transistor to obtain an output signal at the output of the replica transistor. The output signal is mixed with another ...	03/16/2010
7668925	Method and apparatus for routing in SAS using logical zones A method and apparatus are provided for routing in an SAS expander for logical zoning. Common SAS topology defined by the ANSI T10 specification only relates to physical topology with multiple end devices, as well as to expander devices and the broadcast handling me...	02/23/2010
7668210	Method and apparatus for reducing current demand variations in large fan-out trees A method and apparatus are provided for reducing current demand variations in large fanout trees. The fanout tree is split into at least 2 sub-groups, each preferably with substantially equal parasitic capacitance. Data is then scrambled according to a scrambling se...	02/23/2010
7656945	Stabilized digital timing recovery using low-complexity equalizer A low-complexity digital linear equalizer whose operation and adaptation makes stabilized digital timing recovery practical. The technique is fundamental for the operation of communications receivers employing digital timing recovery, e.g., in a modem. A technique f...	02/02/2010
7656791	Systems and methods for hitless equipment protection Disclosed techniques include a method and apparatus that allow traffic to be switched between a working copy and a protected copy hitlessly. The control method simplifies implementation by advantageously distinguishing points within the apparatus wherein the working...	02/02/2010
7656227	Techniques to control amplifier gain over process, voltage, and/or temperature (PVT) variations Methods and apparatus control the gain of an RF amplifier. In an example, the RF amplifier is biased for low distortion. The bias is not changed to adjust gain. Rather, the amplifier's gain is controlled by selectively activating or deactivating RF amplifier cells o...	02/02/2010
7646063	Compact CMOS ESD layout techniques with either fully segmented salicide ballasting (FSSB) in the source and/or drain regions Transistor structures for relatively even current balancing within a device and methods for fabricating the same are disclosed. These devices can be used in relatively compact MOSFET Electrostatic Discharge (ESD) protection structures, such as in snapback devices. O...	01/12/2010
7622987	Pattern-based DC offset correction DC offsets in high-gain amplifiers should be corrected to avoid the signal distortion that would result from amplifier saturation. A predominantly digital technique is described in which a digital algorithm observes patterns in the sign of the amplifier output and d...	11/24/2009
7584319	Connection management in serial attached SCSI (SAS) expanders A method and apparatus are provided for implementing connection management in SAS expander devices. SAS expanders are commonly used within a SAS network topology to allow multiple disk drives to connect to multiple host devices. The method and apparatus provides arb...	09/01/2009
7558357	Systems and methods for reducing frequency-offset induced jitter Methods and apparatus nullify an intrinsic jitter component in a digital clock recovery circuit induced by a time base frequency difference between an incoming data signal and a local synchronization clock for the digital clock recovery circuit. The techniques discl...	07/07/2009
7557626	Systems and methods of reducing power consumption of digital integrated circuits There exists a speed/power tradeoff in many digital logic circuits. In one embodiment, the tradeoff is used to reduce or minimize power dissipation by slowing down digital logic paths as system performance requirements allow. Relatively low power dissipation occurs ...	07/07/2009
7543193	Serial data validity monitor A data detection system includes, in part, a CID detector, a DC balance monitor and a transition density detector. The CID detector is configured to detect whether the received data stream includes a CID exceeding a predetermined threshold count. The DC balance moni...	06/02/2009

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Assignee: PMC-Sierra, Inc.