Bizarre Patents
Mouse device with a built-in printer
A mouse device for use as an input device of a computer is provided that includes a housing in which recording paper is loadable, and a printer unit provided within the housing for printing on the recording paper print information received from the computer.
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| Number | Title | Issue Date |
| 8178876 | Method and configuration for connecting test structures or line arrays for monitoring integrated circuit manufacturing A test chip comprises at least one level having an array of regions. Each region is capable of including at least one test structure. At least some of the regions include respective test structures. The level has a plurality of driver lines that provide input signal... | 05/15/2012 |
| 8082529 | Method and system for mapping a boolean logic network to a limited set of application-domain specific logic cells A method and system is described for mapping a system-level description of an integrated system directly to a technology-specific set of logic cells that are comprised primarily of large complex cells (bricks). The invention is based on applying aggressive Boolean o... | 12/20/2011 |
| 8004315 | Process for making and designing an IC with pattern controlled layout regions The invention provides a reduced complexity layout style based on applying a limited set of changes to an underlying repeated base template. With the templates properly defined in accordance with the characteristic features disclosed, the invention enables efficient... | 08/23/2011 |
| 7969199 | Pattern controlled IC layout The invention provides a reduced complexity layout style based on applying a limited set of changes to an underlying repeated base template. With the templates properly defined in accordance with the characteristic features disclosed, the invention enables efficient... | 06/28/2011 |
| 7935965 | Test structures and methods for electrical characterization of alignment of line patterns defined with double patterning A test vehicle and method for electrical characterization of misalignment, for example resulting from double patterning processes, that enables characterization of patterns on wafers which have finished processing. It includes a structure and method for measurement ... | 05/03/2011 |
| 7906254 | Method and process for design of integrated circuits using regular geometry patterns to obtain geometrically consistent component features The invention provides a method and process for designing an integrated circuit based on using the results from both 1) a specific set of silicon test structure characterizations and 2) the decomposition of logic into combinations of simple logic primitives, from wh... | 03/15/2011 |
| 7894926 | Global predictive monitoring system for a manufacturing facility A global predictive monitoring system for a manufacturing facility. The system may be employed in an integrated circuit (IC) device fabrication facility to monitor processing of semiconductor wafers. The system may include deployment of a swarm of individually separ... | 02/22/2011 |
| 7888961 | Apparatus and method for electrical detection and localization of shorts in metal interconnect lines A test structure for localizing shorts in an integrated circuit and method of testing is described. A first comb structure is formed from a first busbar and a first plurality of fingers extending from the first busbar. A second comb structure formed from a second bu... | 02/15/2011 |
| 7827516 | Method and system for grouping logic in an integrated circuit design to minimize number of transistors and number of unique geometry patterns A method and system are described to group logic terms at a higher level of abstraction than that found using standard cells to implement the logic functions using a reduced number of transistors, and to reduce the total number of unique geometry patterns needed to ... | 11/02/2010 |
| 7807480 | Test cells for semiconductor yield improvement A test cell for localizing defects includes a first active region, a second active region formed substantially parallel to the first active region, a third active region formed substantially parallel to the first and second active regions, a fourth active region for... | 10/05/2010 |
| 7673262 | System and method for product yield prediction A system and method for predicting yield of integrated circuits includes at least one type of characterization vehicle which incorporates at least one feature which is representative of at least one type of feature to be incorporated in the final integrated circuit ... | 03/02/2010 |
| 7644388 | Method for reducing layout printability effects on semiconductor device performance A printability simulation is performed on a mask layout over a range of lithography process conditions. A layout configuration capable of inducing functional or parametric failure in a semiconductor device is identified in the mask layout. A test structure represent... | 01/05/2010 |
| 7638247 | Method for electron beam proximity effect correction Optimized dose assignments are determined for each portion of a layout by utilizing an improved proximity function and additional dose correction functions in performing a short range proximity effect correction. The optimized dose assignments are determined to mini... | 12/29/2009 |
| 7592827 | Apparatus and method for electrical detection and localization of shorts in metal interconnect lines A test structure for localizing shorts in an integrated circuit and method of testing is described. A first comb structure is formed from a first busbar and a first plurality of fingers extending from the first busbar. A second comb structure formed from a second bu... | 09/22/2009 |
| 7527987 | Fast localization of electrical failures on an integrated circuit system and method Fast localization of electrically measured defects of integrated circuits includes providing information for fabricating a test chip having test structures configured for parallel electrical testing. The test structures on the test chip are electrically tested emplo... | 05/05/2009 |
| 7508071 | Adjusting die placement on a semiconductor wafer to increase yield A die placement of dice to be formed on a semiconductor wafer is adjusted by obtaining a die placement and one or more locations on the wafer contacted by one or more processing structures or a substance emitted by one or more processing structures. The die placemen... | 03/24/2009 |
| 7494893 | Identifying yield-relevant process parameters in integrated circuit device fabrication processes In one embodiment, wafers are processed to build test structures in the wafers. The wafers may be processed in tools of process steps belonging to a process module. The test structures may be tested to obtain defectivity data. Tool process parameters may be monitore... | 02/24/2009 |
| 7489151 | Layout for DUT arrays used in semiconductor wafer testing A layout for devices under test formed on a semiconductor wafer for use in wafer testing includes a first array of devices under test and a first pad set formed adjacent to the first array. The first pad set includes a gate force pad, a source pad, and a drain pad. ... | 02/10/2009 |
| 7487474 | Designing an integrated circuit to improve yield using a variant design element An integrated circuit is designed to improve yield when manufacturing the integrated circuit, by obtaining a design element from a set of design elements used in designing integrated circuits. A variant design element is created based on the obtained design element,... | 02/03/2009 |
| 7440869 | Mapping yield information of semiconductor dice In one exemplary embodiment, yield information of semiconductor dice is mapped by obtaining yield information of a first die that was formed on a first location on a first wafer. Yield information is obtained of a second die that was formed on a second location on a... | 10/21/2008 |
| 7434197 | Method for improving mask layout and fabrication A hot spot is identified within a mask layout design. The hot spot represents a local region of the mask layout design having one or more feature geometries susceptible to producing one or more fabrication deficiencies. A test structure is generated for the identifi... | 10/07/2008 |
| 7415386 | Method and system for failure signal detection analysis A method for analyzing a sample of wafers includes identifying F failure metrics applicable to at least one pattern on each wafer within the sample. Z spatial and/or reticle zones are identified on each wafer, where Z and F are integers. Values are provided for each... | 08/19/2008 |
| 7395518 | Back end of line clone test vehicle A test vehicle comprises at least one product layer having a east one product circuit pattern on the product layer, and one or more clone layers formed over the product layer (1902). The one or more clone layers include a plurality of structures, which may in... | 07/01/2008 |
| 7373625 | System and method for product yield prediction A system and method for predicting yield of integrated circuits includes at least one type of characterization vehicle which incorporates at least one feature which is representative of at least one type of feature to be incorporated in the final integrated circuit ... | 05/13/2008 |
| 7356800 | System and method for product yield prediction A system and method for predicting yield of integrated circuits includes at least one type of characterization vehicle which incorporates at least one feature which is representative of at least one type of feature to be incorporated in the final integrated circuit ... | 04/08/2008 |
| 7348594 | Test structures and models for estimating the yield impact of dishing and/or voids A test structure comprising a test pattern is formed on a substrate. The test pattern includes a first comb structure having a plurality of tines, and a second structure. The second structure may be a snake structure having a plurality of side walls or a second comb... | 03/25/2008 |
| 7334205 | Optimization of die placement on wafers A method of optimizing production of semiconductor devices on a wafer comprises steps of characterizing at least one effect of at least one manufacturing component on at least one optimization criterion; inputting user optimization data; and, based on the at least o... | 02/19/2008 |
| 7305638 | Method and system for ROM coding to improve yield A method for improving yield of a process for fabricating a read-only memory (ROM) includes evaluating a yield of a ROM fabrication process associated with a first ROM design. At least two candidate ROM design modifications are identified. At least one of the candid... | 12/04/2007 |
| 7278118 | Method and process for design of integrated circuits using regular geometry patterns to obtain geometrically consistent component features The invention provides a method and process for designing an integrated circuit based on using the results from both 1) a specific set of silicon test structure characterizations and 2) the decomposition of logic into combinations of simple logic primitives, from wh... | 10/02/2007 |
| 7220605 | Selecting dice to test using a yield map Dice on a wafer are selected to be tested using a yield map. The yield map incorporates yield information of different products produced by the same fabrication process. A die placement for a product to be produced by the same process is determined based on the yiel... | 05/22/2007 |
| 7197726 | Test structures for estimating dishing and erosion effects in copper damascene technology A test structure combines a first structure (1010) for erosion evaluation with a second structure (1000) for extraction of defect size distributions. The first structure (1010) is a loop structure usable determine a resistance value that varies ... | 03/27/2007 |
| 7190183 | Selecting die placement on a semiconductor wafer to reduce test time A die placement of dies on a wafer is selected to reduce test time of the dies by obtaining a die placement and determining placements of a tester head needed to test the dies in the die placement. A number of touchdowns needed in the determined placements of the te... | 03/13/2007 |
| 7174521 | System and method for product yield prediction A system and method for predicting yield of integrated circuits includes at least one type of characterization vehicle which incorporates at least one feature which is representative of at least one type of feature to be incorporated in the final integrated circuit ... | 02/06/2007 |
| 7169638 | Adjusting die placement on a semiconductor wafer to increase yield A die placement of dice to be formed on a semiconductor wafer is adjusted by obtaining a die placement and one or more locations on the wafer contacted by one or more processing structures or a substance emitted by one or more processing structures. The die placemen... | 01/30/2007 |
| 7154115 | Zoom in pin nest structure, test vehicle having the structure, and method of fabricating the structure A test vehicle (100) comprises a substrate (99), a plurality of nested serpentine lines (202) on the substrate, and a plurality of test pads (204) on the substrate. Each serpentine line has a plurality of turn sections that comprise two p... | 12/26/2006 |
| 7087507 | Implantation of deuterium in MOS and DRAM devices A structure and method passivates dangling silicon bonds by the introduction of deuterium into a Metal Oxide Semiconductor Field Effect Transistor (MOSFET) by ion implantation. The process of implantation provides precise placement of deuterium at optimum locations ... | 08/08/2006 |
| 7047505 | Method for optimizing the characteristics of integrated circuits components from circuit specifications A method for selecting a process for forming a device, includes generating a plurality of equations using a response surface methodology model. Each equation relates a respective device simulator input parameter to a respective combination of processing parameters t... | 05/16/2006 |
| 7039543 | Transforming yield information of a semiconductor fabrication process Publishable yield information can be produced by obtaining an actual yield value associated with an integrated circuit (IC) or portion of an IC formed on each one of a plurality of wafers using a semiconductor wafer fabrication process. An average yield value associ... | 05/02/2006 |
| 7024642 | Extraction method of defect density and size distributions A characterization vehicle includes a substrate having at least one layer (300), and a plurality of pairs of nested serpentine lines on a single surface of a single layer of the substrate (301a . . . 301h, 302a . .... | 04/04/2006 |
| 7003742 | Methodology for the optimization of testing and diagnosis of analog and mixed signal ICs and embedded cores A method for analyzing an integrated circuit (IC) having at least one of the group consisting of digital and analog components, where the IC is designed to meet a plurality of circuit performance specifications, and fabrication of the IC is monitored by measuring pr... | 02/21/2006 |
