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| Number | Title | Issue Date |
| 8178443 | Hardmask materials Hardmask films having high hardness and low stress are provided. In some embodiments a film has a stress of between about −600 MPa and 600 MPa and hardness of at least about 12 GPa. In some embodiments, a hardmask film is prepared by depositing multiple sub-layers... | 05/15/2012 |
| 8173537 | Methods for reducing UV and dielectric diffusion barrier interaction Stability of an underlying dielectric diffusion barrier during deposition and ultraviolet (UV) processing of an overlying dielectric layer is critical for successful integration. UV-resistant diffusion barrier layers are formed by depositing the layer in a hydrogen-... | 05/08/2012 |
| 8172992 | Wafer electroplating apparatus for reducing edge defects Methods, apparatuses, and various apparatus components, such as base plates, lipseals, and contact ring assemblies are provided for reducing contamination of the contact area in the apparatuses. Contamination may happen during removal of semiconductor wafers from ap... | 05/08/2012 |
| 8172646 | Magnetically actuated chuck for edge bevel removal Provided are magnetically actuated wafer chucks that permit a wafer to be clamped or unclamped at any time during a process and at any rotational speed, as desired. Such wafer chucks may include constraining members that are movable between open and closed positions... | 05/08/2012 |
| 8168540 | Methods and apparatus for depositing copper on tungsten Apparatus and methods for depositing copper on tungsten are presented. The invention finds particular use in the semiconductor industry for depositing copper seed layers onto fields or through silicon vias having tungsten barrier layers, both reducing cost and compl... | 05/01/2012 |
| 8158532 | Topography reduction and control by selective accelerator removal Plating accelerator is applied selectively to a substantially-unfilled wide (e.g., low-aspect-ratio feature cavity. Then, plating of metal is conducted to fill the wide feature cavity and to form an embossed structure in which the height of a wide-feature metal prot... | 04/17/2012 |
| 8156892 | Edge profiling for process chamber shields Process chamber shields having specially profiled edges exhibit increased lifetime in PVD and CVD deposition chambers. Edge profiling reduces flaking and delamination of materials deposited onto the shields, thereby prolonging shield life, and, consequently, reducin... | 04/17/2012 |
| 8153520 | Thinning tungsten layer after through silicon via filling Methods of processing partially manufactured semiconductor substrates with one or more through silicon vias to partially remove a tungsten layer formed on the field region during filling the through silicon vias are provided. In certain embodiments, the methods prod... | 04/10/2012 |
| 8147660 | Semiconductive counter electrode for electrolytic current distribution control A semiconductive counter electrode covers a highly electronically conductive electric current buss. The semiconductive counter electrode is impervious to ion flow. A substrate holder is operable to hold a substrate and to form a thin fluid gap between the semiconduc... | 04/03/2012 |
| 8137467 | Temperature controlled showerhead A temperature controlled showerhead for chemical vapor deposition (CVD) chambers enhances heat dissipation to enable accurate temperature control with an electric heater. Heat dissipates by conduction through a showerhead stem and fluid passageway and radiation from... | 03/20/2012 |
| 8137465 | Single-chamber sequential curing of semiconductor wafers The present invention relates to curing of semiconductor wafers. More particularly, the invention relates to cure chambers containing multiple cure stations, each featuring one or more UV light sources. The wafers are cured by sequential exposure to the light source... | 03/20/2012 |
| 8133797 | Protective layer to enable damage free gap fill In-situ semiconductor process that can fill high aspect ratio (typically at least 6:1, for example 7:1 or higher), narrow width (typically sub 0.13 micron, for example 0.1 micron or less) gaps without damaging underlying features and little or no incidence of voids ... | 03/13/2012 |
| 8129281 | Plasma based photoresist removal system for cleaning post ash residue A method of cleaning a low dielectric constant film in a lithographic process includes providing a dielectric film having thereover a resist composition, the dielectric film having a dielectric constant no greater than about 4.0, and stripping the resist composition... | 03/06/2012 |
| 8129270 | Method for depositing tungsten film having low resistivity, low roughness and high reflectivity Top-down methods of increasing reflectivity of tungsten films to form films having high reflectivity, low resistivity and low roughness are provided. The methods involve bulk deposition of tungsten followed by a removing a top portion of the deposited tungsten. In p... | 03/06/2012 |
| 8128791 | Control of electrolyte composition in a copper electroplating apparatus In a copper electroplating apparatus having separate anolyte and catholyte portions, the concentration of anolyte components (e.g., acid or copper salt) is controlled by providing a diluent to the recirculating anolyte. The dosing of the diluent can be controlled by... | 03/06/2012 |
| 8128461 | Chemical mechanical polishing with multi-zone slurry delivery Chemical-mechanical polishing or planarization (CMP) is enhanced with multi-zone slurry delivery. A polishing pad is provided that contacts with the work piece, and a multi-zone platen is displaced proximate to the polishing pad to facilitate slurry delivery. The pl... | 03/06/2012 |
| 8124531 | Depositing tungsten into high aspect ratio features Methods and apparatuses for filling high aspect ratio features with tungsten-containing materials in a substantially void-free manner are provided. In certain embodiments, the method involves depositing an initial layer of a tungsten-containing material followed by ... | 02/28/2012 |
| 8124522 | Reducing UV and dielectric diffusion barrier interaction through the modulation of optical properties Provided are methods of stabilizing an underlying dielectric diffusion barrier during deposition and ultraviolet (UV) processing of an overlying dielectric layer. Methods include modulating the optical properties reduces the effects of UV radiation on the dielectric... | 02/28/2012 |
| 8120376 | Fault detection apparatuses and methods for fault detection of semiconductor processing tools Fault detection apparatuses and methods for detecting a processing or hardware performance fault of a semiconductor production tool have been provided. In an exemplary embodiment, a method for detecting a fault of a semiconductor production tool includes sensing a s... | 02/21/2012 |
| 8119527 | Depositing tungsten into high aspect ratio features Methods of filling high aspect ratio features provided on partially manufactured semiconductor substrates with tungsten-containing materials are provided. In certain embodiments, the methods include partial filling a high aspect ratio feature with a layer of tungste... | 02/21/2012 |
| 8114782 | Method for etching organic hardmasks A method of etching or removing an amorphous carbon organic hardmask overlying a low dielectric constant film in a lithographic process. The method includes providing a dielectric film having thereover an amorphous carbon organic hardmask to be removed, the dielectr... | 02/14/2012 |
| 8110493 | Pulsed PECVD method for modulating hydrogen content in hard mask A method for forming a PECVD deposited amorphous carbon or ashable hard mask (AHM) in a trench or a via with less than 30% H content at a process temperature below 500° C., e.g., about 400° C. produces low H content hard masks with high selectivity and little or n... | 02/07/2012 |
| 8110068 | Gas flow distribution receptacles, plasma generator systems, and methods for performing plasma stripping processes Systems, system components, and methods for plasma stripping are provided. In an embodiment, a gas flow distribution receptacle may have a rounded section that includes an inner surface defining a reception cavity, an outer surface forming an enclosed end, and a cen... | 02/07/2012 |
| 8106651 | Methods and apparatuses for determining thickness of a conductive layer Methods and apparatuses for calibrating eddy current sensors. A calibration curve is formed relating thickness of a conductive layer in a magnetic field to a value measured by the eddy current sensors or a value derived from such measurement, such as argument of imp... | 01/31/2012 |
| 8101531 | Plasma-activated deposition of conformal films Methods and hardware for depositing thin conformal films using plasma-activated conformal film deposition (CFD) processes are described herein. In one example, a method for forming a thin conformal film comprises, in a first phase, generating precursor radicals off ... | 01/24/2012 |
| 8101521 | Methods for improving uniformity and resistivity of thin tungsten films The methods described herein relate to deposition of low resistivity, highly conformal tungsten nucleation layers. These layers serve as a seed layers for the deposition of a tungsten bulk layer. The methods are particularly useful for tungsten plug fill in which tu... | 01/24/2012 |
| 8100081 | Edge removal of films using externally generated plasma species The present invention provides methods and apparatuses for removing unwanted film from the edge area of substrate using remotely-generated plasmas. Activated plasma species are directed to the edge of the substrate to contact and remove the unwanted film, while intr... | 01/24/2012 |
| 8099192 | Method and apparatus for teaching a workpiece transfer robot A method is provided for teaching a transfer robot used in conjunction with a workpiece processing system including a pedestal assembly, a light sensor having an optical input fixedly coupled to the pedestal assembly, a transfer robot having an end effector, and a p... | 01/17/2012 |
| 8084339 | Remote plasma processing of interface surfaces Embodiments related to the cleaning of interface surfaces in a semiconductor wafer fabrication process via remote plasma processing are disclosed herein. For example, in one disclosed embodiment, a semiconductor processing apparatus includes a processing chamber, a ... | 12/27/2011 |
| 8082044 | Apparatus and methods for precompiling program sequences processing for wafer processing Disclosed are apparatus and methods for embodiments for efficiently and flexibly controlling hardware devices in a semiconductor processing system are provided for use in a distributed control arrangement. In general, the distributed arrangement includes at least on... | 12/20/2011 |
| 8076241 | Methods for multi-step copper plating on a continuous ruthenium film in recessed features Methods are provided for multi-step Cu metal plating on a continuous Ru metal film in recessed features found in advanced integrated circuits. The use of a continuous Ru metal film prevents formation of undesirable micro-voids during Cu metal filling of high-aspect-... | 12/13/2011 |
| 8062983 | Creation of porosity in low-k films by photo-disassociation of imbedded nanoparticles Porous dielectric layers are produced by embedding and removing nanoparticles in composite dielectric layers. The pores may be produced after the barrier material, the metal or other conductive material is deposited to form a metallization layer. In this manner, the... | 11/22/2011 |
| 8062977 | Ternary tungsten-containing resistive thin films Heater elements made of high resistivity ternary and quaternary thin films containing three or more of W, C, O, N and Si are provided. The thin films have resistivities at least about 1000 μΩ-cm at 50 to 60 Angstroms. The ternary and quaternary films have improved... | 11/22/2011 |
| 8060252 | High throughput method of in transit wafer position correction in system using multiple robots Methods correcting wafer position error are provided. The methods involve measuring wafer position error on a robot, e.g. a dual side-by-side end effector robot, during transfer to an intermediate station. This measurement data is then used by a second robot to perf... | 11/15/2011 |
| 8058181 | Method for post-etch cleans The current invention provides methods for performing a cleaning process that provides greater cleaning efficiency with less damage to device structures. After etching and photoresist stripping, a first plasma clean is performed. The first plasma clean may comprise ... | 11/15/2011 |
| 8058179 | Atomic layer removal process with higher etch amount Higher overall etch rate and throughput for atomic layer removal (ALR) is achieved. The reaction is a self-limiting process, thus limiting the total amount of material that may be etched per cycle. By pumping down the process station between reacting operations, the... | 11/15/2011 |
| 8058178 | Photoresist strip method for low-k dielectrics The present invention pertains to methods for removing unwanted material from a semiconductor wafer during wafer manufacturing. More specifically, the invention pertains to stripping photo-resist material and removing etch-related residues from a semiconductor wafer... | 11/15/2011 |
| 8058170 | Method for depositing thin tungsten film with low resistivity and robust micro-adhesion characteristics Methods of forming low resistivity tungsten films with good uniformity and good adhesion to the underlying layer are provided. The methods involve forming a tungsten nucleation layer using a pulsed nucleation layer process at low temperature and then treating the de... | 11/15/2011 |
| 8055370 | Apparatus and methods for monitoring health of semiconductor process systems Disclosed are apparatus and methods for monitoring an operation parameter of a process tool, independently of a process system recipe, are provided. In general, an indirect effect that results from implementing an event from a process system recipe on the process sy... | 11/08/2011 |
| 8053861 | Diffusion barrier layers Provided are methods and apparatuses for depositing barrier layers for blocking diffusion of conductive materials from conductive lines into dielectric materials in integrated circuits. The barrier layer may contain copper. In some embodiments, the layers have condu... | 11/08/2011 |
