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Walt Disney was no Mickey Mouse inventor. He devised a serious animation camera which he patented. With the device, his company created "Snow White".
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| Number | Title | Issue Date |
| 5877975 | Insertable/removable digital memory apparatus and methods of operation thereof Each device of a family of removable digital media devices (310, 320, 330, 340, 350 and 360) may be plugged into a host to permits the host to store data in it or to retrieve data from it. The form factors of the digital media devices in the family and th... | 03/02/1999 |
| 5819069 | Recording apparatus and method having low power consumption A low power recording devices permits various flexible power options, including a no-battery option in which the recording device satisfies its entire power requirements from the telephone wall socket and from the RS-232 socket of a computer, and a no-bat... | 10/06/1998 |
| 5815426 | Adapter for interfacing an insertable/removable digital memory apparatus to a host data part Each device of a family of removable digital media devices (310, 320, 330, 340, 350 and 360) may be plugged into a host to permits the host to store data in it or to retrieve data from it. The form factors of the digital media devices in the family and th... | 09/29/1998 |
| 5724303 | Non-volatile programmable memory having an SRAM capability A computer system includes a computing device such as a microcontroller and a memory device. The memory device is illustrtively a serial device connected to the serail port of the microcontrollerThe memory device includes a page latch load circuit which p... | 03/03/1998 |
| 5563842 | Row decoder for a memory having settable threshold memory cells A memory (1) operative in an erase mode, a program mode, or a read mode includes a memory cell array, word lines (30, 40, 50, 60), a row decoder (9) connected to the word lines, bit lines (2, 4, 6, 8), a precharge circuit (70, 72, 74, 76, 78, 80) connecte... | 10/08/1996 |
| 5508955 | Electronically erasable-programmable memory cell having buried bit line A memory cell (510) suitable for an array of memory cells (100) has a source that is part of a buried bit line and a drain that is part of an adjacent buried bit line. The memory cell also includes a split gate arrangement (580) in which the gate is integ... | 04/16/1996 |
| 5414658 | Electrically erasable programmable read-only memory array A memory (1) operative in an erase mode, a program mode, or a read mode includes a memory cell array, word lines (30, 40, 50, 60), a row decoder (9) connected to the word lines, bit lines (2, 4, 6, 8), a precharge circuit (70, 72, 74, 76, 78, 80) connecte... | 05/09/1995 |
| 5410680 | Solid state memory device having serial input/output A magnetic media hard disk is emulated in a solid state hard disk having a disk controller, a data buffer, a microcontroller, and a disk emulator section. The disk emulator section includes a disk emulator interface and a memory array. The architecture of... | 04/25/1995 |
| 5408431 | Single transistor EEPROM architecture A single-transistor EEPROM device of the present invention comprises memory transistors in banks similar to NAND structures wherein the control gates of the memory transistors have negative voltages applied in various modes that allow reading, writing, an... | 04/18/1995 |
| 5357465 | Single transistor EEPROM memory cell A single-transistor non-volatile memory cell MOS transistor with a floating gate and a control gate using two levels of polysilicon and a tunnel dielectric that overlaps the drain area wherein a tunneling of charge can take place between the drain and the... | 10/18/1994 |
| 5345418 | Single transistor EEPROM architecture A single-transistor EEPROM device of the present invention comprises memory transistors in banks similar to NAND structures wherein the control gates of the memory transistors have negative voltages applied in various modes that allow reading, writing, an... | 09/06/1994 |
| 5323351 | Method and apparatus for programming electrical erasable programmable read-only memory arrays A method of controllably programming an electrically erasable programmable read only memory comprises the step of erasing a group of memory cells of the memory into a high threshold state. The group including data cells and monitor cells. The data cells o... | 06/21/1994 |
| 5297081 | Electrical erasable programmable read-only memory array A memory (1) operative in an erase mode, a program mode, or a read mode includes a memory cell array, word lines (30, 40, 50, 60), a row decoder (9) connected to the word lines, bit lines (2, 4, 6, 8), a precharge circuit (70, 72, 74, 76, 78, 80) connecte... | 03/22/1994 |
| 5291584 | Methods and apparatus for hard disk emulation A magnetic media hard disk is emulated in a solid state hard disk having a disk controller, a data buffer, a microcontroller, and a disk emulator section. The disk emulator section includes a disk emulator interface and a memory array. The architecture of... | 03/01/1994 |
| 5222040 | Single transistor EEPROM memory cell A single-transistor non-volatile memory cell MOS transistor with a floating gate and a control gate using two levels of polysilicon and a tunnel dielectric that overlaps the drain area wherein a tunneling of charge can take place between the drain and the... | 06/22/1993 |
| 5197027 | Single transistor EEPROM architecture A single-transistor EEPROM device of the present invention comprises memory transistors in banks similar to NAND structures wherein the control gates of the memory transistors have negative voltages applied in various modes that allow reading, writing, an... | 03/23/1993 |
