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| Number | Title | Issue Date |
| 7961723 | Advanced processor with mechanism for enforcing ordering between information sent on two independent networks An advanced processor comprises a plurality of multithreaded processor cores each having a data cache and instruction cache. A data switch interconnect is coupled to each of the processor cores and configured to pass information among the processor cores. A messagin... | 06/14/2011 |
| 7864760 | Advanced processor with mechanism for enforcing ordering between information sent on two independent networks An advanced processor comprises a plurality of multithreaded processor cores each having a data cache and instruction cache. A data switch interconnect is coupled to each of the processor cores and configured to pass information among the processor cores. A messagin... | 01/04/2011 |
| 7840783 | System and method for performing a register renaming operation utilizing hardware which is capable of operating in at least two modes utilizing registers of multiple widths A system, method, and computer program product are provided for performing a register renaming operation utilizing hardware which operates in at least two modes. In operation, hardware is operated in at least two modes including a first mode for operating the hardwa... | 11/23/2010 |
| 7835334 | Output queued switch with a parallel shared memory, and method of operating same A network switch includes an input layer to receive a data stream with a set of cells. Each cell includes data and a header to designate a destination device. The input layer includes a set of input layer circuits. A selected input layer circuit of the set of input ... | 11/16/2010 |
| 7826477 | Advanced telecommunications router and crossbar switch controller The invention relates to a crossbar switch controller including an input terminal configured to receive a set of service request signals from a set of virtual output queues each comprising a set of packets. The invention also includes a matrix circuit coupled to the... | 11/02/2010 |
| 7797509 | Systems and methods for utilizing an extended translation look-aside buffer having a hybrid memory structure Extended translation look-aside buffers (eTLB) for converting virtual addresses into physical addresses are presented, the eTLB including, a physical memory address storage having a number of physical addresses, a virtual memory address storage configured to store a... | 09/14/2010 |
| 7747599 | Integrated search engine devices that utilize hierarchical memories containing b-trees and span prefix masks to support longest prefix match search operations A search engine device includes a hierarchical memory that is configured to store a b-tree of search prefixes and span prefix masks (SPMs). These SPMs are evaluated during each search operation to identify search prefixes that match an applied search key yet reside ... | 06/29/2010 |
| 7725450 | Integrated search engine devices having pipelined search and tree maintenance sub-engines therein that maintain search coherence during multi-cycle update operations A search engine includes a pipelined arrangement of a plurality of search and tree maintenance sub-engines therein, which are configured to support the performance of search operations on exclusively valid multi-way trees of search prefixes concurrently with the per... | 05/25/2010 |
| RE41351 | CAM arrays having CAM cells therein with match line and low match line connections and methods of operating same A CAM array including volatile or non-volatile ternary CAM cells that discharge their associated match line through a special discharge line (e.g., a low match line), instead of through the bit line, is disclosed. Each ternary CAM cell includes a pair of storage ele... | 05/25/2010 |
| 7716204 | Handle allocation managers and methods for integated circuit search engine devices A handle allocation manager is provided for an integrated circuit search engine device that includes multiple stages of a multilevel tree of search keys and a handle memory. The handle allocation manager includes a handle availability memory that stores handle avail... | 05/11/2010 |
| 7711935 | Universal branch identifier for invalidation of speculative instructions A system for speculative branch predictions. An embodiment of the system includes branch prediction logic, fetch logic, and branch identification logic. The branch prediction logic is configured to predict a branch path for a branch in an instruction stream. The fet... | 05/04/2010 |
| 7711893 | Range code compression method and apparatus for ternary content addressable memory (CAM) devices A content addressable memory (CAM) device, method, and method of generating entries for range matching are disclosed. A CAM device (800) according to one embodiment can include a pre-encoder (806) that encodes range bit values W into additional bits E.... | 05/04/2010 |
| 7697518 | Integrated search engine devices and methods of updating same using node splitting and merging operations Methods of updating b-tree data structures (e.g., b*tree data structure) using search key insertion and deletion operations proceed from respective known states (e.g., respective canonical forms). These insertion operations include inserting a first search key into ... | 04/13/2010 |
| 7694068 | Re-entrant processing in a content addressable memory A processing system includes a network processor and a CAM device having a re-entrant processor coupled to a CAM array. The re-entrant processor is configured to selectively modify an initial search key provided by the network processor by replacing portions of the ... | 04/06/2010 |
| 7692941 | Separate CAM core power supply for power saving A CAM system includes an integrated circuit chip having: logic & control circuitry, a CAM cell array, read/write access circuitry that performs read and write accesses to the CAM cell array, comparison access circuitry that performs comparison operations to the CAM ... | 04/06/2010 |
| 7688609 | Content addressable memory having dynamic match resolution A content addressable memory (CAM) architecture. For one embodiment, the CAM architecture includes a plurality of rows of CAM cells, each row configured to generate match results on a corresponding match line, a number of comparand lines, each coupled to a correspon... | 03/30/2010 |
| 7685480 | Content addressable memory having redundant row isolated noise circuit and method of use A system and method are provided for reducing the capacitive coupling noise on a fuse line of a content addressable memory (CAM) system. The CAM system includes a plurality of CAM arrays having a plurality of rows of CAM cells to store data coupled to wordlines, sea... | 03/23/2010 |
| 7685039 | Cost-based technology and manufacturing exchange Cost-based methods of exchanging/transferring intellectual property (IP) among parties are provided that include royalty rates and mark-up rates based on a common factor. The common factor of an embodiment includes the cost of a component material of a product. The ... | 03/23/2010 |
| 7684426 | System and method for performing concatentation of diversely routed channels A system and method are provided for performing Local Center Authorization Service (LCAS) in a network system, the system having a data aligner configured to align bytes of input data according to groups of members. The system also including an LCAS control manager ... | 03/23/2010 |
| 7679345 | Digital linear voltage regulator A digital linear voltage regulator includes a comparator, a finite state machine, and a current digital-to-analog converter (DAC). The comparator is preferably coupled to receive a reference voltage and an operating voltage supplied to a dynamic load. The comparator... | 03/16/2010 |
| 7676444 | Iterative compare operations using next success size bitmap A search engine for selectively perform iterative compare operations between a searchable pattern and S overlapping substrings of an input string of characters includes a memory for storing a bitmap having S next success size (NSS) bits, wherein each NSS bit indicat... | 03/09/2010 |
| 7669005 | Content addressable memory (CAM) devices having soft priority resolution circuits therein and methods of operating same Content addressable memory (CAM) devices use both hard and soft priority techniques to allocate entries of different priority therein. The priorities of multiple CAM array blocks within the CAM device may be programmed before or as entries are loaded therein and may... | 02/23/2010 |
| 7668089 | Method and apparatus for terminating selected traffic flows A traffic management processor configured to selectively terminate individual traffic flows includes an instruction decoder to receive a termination instruction specifying which traffic flows are to be deleted, and a content addressable memory device having a plural... | 02/23/2010 |
| 7660140 | Content addresable memory having selectively interconnected counter circuits A content addressable memory (CAM) device includes a plurality of CAM rows, a number of sequencing logic circuits, and a programmable interconnect structure. Each CAM row includes a number of CAM cells to generate a match signal on a match line and includes an enabl... | 02/09/2010 |
| 7653619 | Integrated search engine devices having pipelined search and tree maintenance sub-engines therein that support variable tree height A pipelined search engine device, such as a longest prefix match (LPM) search engine device, includes a hierarchical memory and a pipelined tree maintenance engine therein. The hierarchical memory is configured to store a b-tree of search prefixes (and possibly span... | 01/26/2010 |
| 7644080 | Method and apparatus for managing multiple data flows in a content search system A content search system for determining whether a plurality of input strings each belonging to any one of a number of different process flows matches one or more of a plurality of regular expressions, including a search circuit for searching the input strings for th... | 01/05/2010 |
| 7643353 | Content addressable memory having programmable interconnect structure A content addressable memory (CAM) device includes a CAM array, a programmable interconnect structure, and a priority encoder. The CAM array includes a plurality of CAM rows, each row including a number of CAM cells for storing a data word and coupled to a match lin... | 01/05/2010 |
| 7636717 | Method and apparatus for optimizing string search operations A search tree embodying a plurality of signatures to be compared with an input string of characters and including a number of success transitions characterized by a success size parameter and including a number of failure transitions characterized by a failure size ... | 12/22/2009 |
| 7634500 | Multiple string searching using content addressable memory A method and apparatus for multiple string searching using a ternary content addressable memory. For one embodiment, the method includes receiving a text string having a plurality of characters and performing an unanchored search of a database of a stored patterns m... | 12/15/2009 |
| 7624226 | Network search engine (NSE) and method for performing interval location using prefix matching A communication network, networking device and method is provided herein for locating (i.e., searching for) an interval of numbers i within a set of numbers N given a point P. The search algorithm provided herein provides fast search speed (e.g., requires only one m... | 11/24/2009 |
| 7624105 | Search engine having multiple co-processors for performing inexact pattern search operations A search engine configured to determine whether an input string including a plurality of input characters matches a regular expression including an inexact pattern including a specified range of instances of pattern characters each belonging to a specified set of ch... | 11/24/2009 |
| 7616571 | Method and apparatus for calculating packet departure times A traffic management processor for scheduling packets for transmission across a network includes a departure time calculator for generating a departure time for each packet, a departure time prioritizer for comparing the departure times with each other to determine ... | 11/10/2009 |
| 7613755 | Signature searching system In a signature searching system, contents of a ternary content addressable memory (CAM) are searched to obtain a first index value that corresponds to a first group of predetermined data sequences. The first group of predetermined data sequences is selected from amo... | 11/03/2009 |
| 7610269 | Method and apparatus for constructing a failure tree from a search tree A method for representing a search tree embodying a plurality of signatures to be searched for in an input string of characters constructs a failure tree in which the states are re-organized in levels according to the number of failure transitions between each state... | 10/27/2009 |
| 7603346 | Integrated search engine devices having pipelined search and b-tree maintenance sub-engines therein A pipelined search engine device, such as a longest prefix match (LPM) search engine device, includes a hierarchical memory and a pipelined tree maintenance engine therein. The hierarchical memory is configured to store a b−tree of search prefixes (and possibly sp... | 10/13/2009 |
| RE40932 | Content addressable memory (CAM) devices that perform pipelined multi-cycle look-up operations using cam sub-arrays and longest match detection A CAM system is provided for determining which data word in a CAM array exhibits the longest continuous, unmasked match with an input data value. The input data value is divided into non-overlapping subfields, thereby creating a series of keys, the first key of the ... | 10/06/2009 |
| 7589362 | Configurable non-volatile logic structure for characterizing an integrated circuit device An integrated circuit (IC) device including a substrate, a plurality of device layers formed over the substrate, and a plurality of multi-level revision (MLR) structures that generate a revision code indicative of device revisions. Each MLR group structure includes ... | 09/15/2009 |
| 7581059 | Controlling a searchable range within a network search engine Controlling a searchable range within a network search engine. A CAM array is provided within the network search engine to store data values in entries having respective addresses and to compare the data values with a search key. First address and a second addresses... | 08/25/2009 |
| 7577784 | Full-ternary content addressable memory (CAM) configurable for pseudo-ternary operation A ternary content addressable memory (TCAM) system and method of operating the same can enable a user to configure the system to operate as either a pseudo TCAM or full TCAM system. Control logic (206) can have an address modification circuit (250) cou... | 08/18/2009 |
| 7571156 | Network device, storage medium and methods for incrementally updating a forwarding database Network devices, storage mediums and methods for updating a memory structure in a data plane of the network device when route updates are received in the control plane of the network device. The methods described herein can be used to perform one of the following al... | 08/04/2009 |
