"I think there is a world market for maybe five computers."
Thomas Watson, chairman of IBM ; 1943
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| Number | Title | Issue Date |
| 7422952 | Method of forming a BJT with ESD self protection A ballasting region is placed between the base region and the collector contact of a bipolar junction transistor to relocate a hot spot away from the collector contact of the transistor. Relocating the hot spot away from the collector contact prevents the collector ... | 09/09/2008 |
| 7372392 | Charge balancing method in a current input ADC A method for charge balancing in a current input ADC including maintaining a low capacitance value at the integrator output node where the capacitance value is independent of the integrator output voltage and operating conditions, generating a first voltage pedestal... | 05/13/2008 |
| 6490606 | Rounding denormalized numbers in a pipelined floating point unit without pipeline stalls For use in a processor having a floating point unit (FPU) capable of managing denormalized numbers in floating point notation, logic circuitry for, and a method of, generating least significant (L), round (R) and sticky (S) bits for a denormalized number.... | 12/03/2002 |
| 6415343 | Apparatus and method for initializing a universal serial bus device A method and apparatus for dynamically assigning and enabling a unique functional address for a Universal Serial Bus device. A host assigns the unique functional address during a control transaction. The Universal Serial Bus device disables the default ad... | 07/02/2002 |
| 5966607 | Metal salicide process employing ion metal plasma deposition A process for forming metal salicide layers on an MOS transistor structure that reduces the risk of forming metal silicide bridges between source/drain regions and a polysilicon gate. The process includes the use of a uni-directional ion metal plasma depo... | 10/12/1999 |
| 4974046 | Bipolar transistor with polysilicon stringer base contact There is disclosed herein a base and emitter contact structure for a bipolar transistor which is comprised of a polysilicon stripe over an isolation island which stripe extends to a position external to the position of the isolation island and assumes the... | 11/27/1990 |
| 4931665 | Master slave voltage reference circuit A circuit for providing a voltage reference level using a master circuit and a plurality of slave circuits. The master circuit includes a Vbb reference circuit, a temperature compensation and Vcse reference circuit, and a voltage ste... | 06/05/1990 |