Did You Know...
...that several people are credited with the invention of the flush toilet? Most people have heard of Thomas Crapper (1837-1910), the sanitary engineer who invented the valve-and-siphon arrangement that made the modern toilet possible. Another claimant to "the throne" was British inventor Alexander Cumming who patented a toilet in 1775. Then there's a nameless Minoan (a native of ancient Crete) who lived 4,000 years ago who supposedly was ahead of his time and created the first flush toilet!
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| Number | Title | Issue Date |
| 7962808 | Method and system for testing the compliance of PCIE expansion systems The present application describes a method and system for testing the compliance of a PCIE expansion system to verify that data signals transmitted through multiple data lanes in the expansion system comply with the PCIE requirements. The method for testing a PCIE e... | 06/14/2011 |
| 7961197 | Method and apparatus for display image adjustment Method and apparatus for display image adjustment is described. More particularly, handles associated with polygon vertices of a polygon rendered image are provided as a graphical user interface (GUI). These handles may be selected and moved by a user with a cursor ... | 06/14/2011 |
| 7961192 | Multi-graphics processor system and method for processing content communicated over a network for display purposes A system and method are provided including a first graphic processor in communication with a content source. In operation, the first graphics processor is adapted for processing content from the content source. Further included is a second graphics processor in comm... | 06/14/2011 |
| 7944452 | Methods and systems for reusing memory addresses in a graphics system Methods and systems for reusing memory addresses in a graphics system are disclosed, so that instances of address translation hardware can be reduced. One embodiment of the present invention sets forth a method, which includes mapping a footprint in screen space to ... | 05/17/2011 |
| 7558348 | Radio frequency antenna system and high-speed digital data link to reduce electromagnetic interference for wireless communications A radio frequency antenna system and high-speed digital data link are disclosed to, among other things, reduce electromagnetic interference (“EMI”) at relatively high data rates while reducing the manufacturing complexities associated with conventional data link... | 07/07/2009 |
| 7554546 | Stippled lines using direct distance evaluation Stippled lines are drawn by evaluating a distance function for a set of points within the area of a stippled line. The distance function gives a distance value proportional to the distance from a point to the end of the stippled line. Using the point's distance valu... | 06/30/2009 |
| 7554538 | Video processing, such as for hidden surface reduction or removal Embodiments of methods, apparatuses, devices, and/or systems for video processing, such as for hidden surface removal or reduction, are described. ... | 06/30/2009 |
| 7551442 | Embedded heat pipe in a hybrid cooling system One embodiment of a system for cooling a heat-generating device includes a base adapted to be coupled to the heat-generating device, a housing coupled to the base, a liquid channel formed between the base and the housing, where a heat transfer liquid may be circulat... | 06/23/2009 |
| 7549596 | Image bearing surface An image bearing surface. In accordance with a first embodiment of the present invention, an image bearing surface comprises a surface for interacting with a writing element of an electronic interactive device to embody a user created image thereon. The image bearin... | 06/23/2009 |
| 7548740 | Variable frequency clock generator for synchronizing data rates between clock domains in radio frequency wireless communication systems A system, method and system are disclosed for using a variable frequency clock generator to synchronize an average data rate over intervals of time in a variable clock domain to make it equal to a fixed data rate in a fixed clock domain while reducing electromagneti... | 06/16/2009 |
| 7548238 | Computer graphics shader systems and methods Methods and systems are described that unite various shading applications under a single language, enable the simple re-use and re-purposing of shaders, facilitate the design and construction of shaders without need for computer programming, and enable the graphical... | 06/16/2009 |
| 7548178 | Method and apparatus for ADC size and performance optimization A sigma delta analog-to-digital converter (ADC) to convert an analog converter input signal to a digital converter output signal. Multiple integrator stages, including at least a first and a final one, each receive an analog input signal and an analog feedback signa... | 06/16/2009 |
| 7546483 | Offloading RAID functions to a graphics coprocessor Systems and methods for using a graphics processor to perform RAID parity functions may improve disk access performance. A method is provided for configuring a graphics processor to perform XOR parity computations when data is written to the RAID array. Another meth... | 06/09/2009 |
| 7546307 | Virtual block storage to filesystem translator A system for a block storage client to work with data blocks in a virtual filesystem (VFS) where the actual data for the data blocks is stored in a real filesystem (RFS). A virtual block mapping table caches references to the actual data in files and directory struc... | 06/09/2009 |
| 7545984 | Quantifying graphics image difference Methods, apparatuses, and systems are presented for measuring difference between graphics images relating to performing an arithmetic operation involving a first graphics image comprising a plurality of first pixels and a second graphics image comprising a plurality... | 06/09/2009 |
| 7545741 | Technique for identifying a failed network interface card within a team of network interface cards One embodiment of the present invention is a method for identifying a faulty NIC in a team of NICs using a minimum number of packets transmitted in a round-robin scheme. Relative to prior art schemes, the disclosed method advantageously reduces the number of keep-al... | 06/09/2009 |
| 7545382 | Apparatus, system, and method for using page table entries in a graphics system to provide storage format information for address translation A graphics system utilizes page table entries to provide information on the storage format used to store graphics data. The page table entries, in turn, may be used for address translation. Exemplary kinds of storage format information include compression mode, a pa... | 06/09/2009 |
| 7545380 | Sequencing of displayed images for alternate frame rendering in a multi-processor graphics system Method, apparatuses, and systems are presented for processing an ordered sequence of images for display using a display device, involving operating a plurality of graphics devices, including at least one first graphics device that processes certain ones of the order... | 06/09/2009 |
| 7543136 | System and method for managing divergent threads using synchronization tokens and program instructions that include set-synchronization bits One embodiment of a computing system configured to manage divergent threads in a thread group includes a stack configured to store at least one token and a multithreaded processing unit. The multithreaded processing unit is configured to perform the steps of fetchin... | 06/02/2009 |
| 7543110 | Raid controller disk write mask A RAID disk array controller implements a write mask to support partial-stripe updates from a host system without expensive RAM to RAM copying and repeated disk accesses to assemble the updated stripe. New data from the host is transferred into a single buffer and a... | 06/02/2009 |
| 7542749 | Variable frequency clock generator for synchronizing data rates between clock domains in radio frequency wireless communication systems A system, method and system are disclosed for using a variable frequency clock generator to synchronize an average data rate over intervals of time in a variable clock domain to make it equal to a fixed data rate in a fixed clock domain while reducing electromagneti... | 06/02/2009 |
| 7542292 | System for efficiently cooling a processor One embodiment of a system for efficiently cooling a processor includes an active hybrid heat transport module adapted to be integrated with a fansink. The hybrid heat transport module comprises both a fluid channel and an air channel adapted for transporting heat. ... | 06/02/2009 |
| 7542046 | Programmable clipping engine for clipping graphics primitives An apparatus, system, and method for clipping graphics primitives are described. In one embodiment, a graphics processing apparatus includes a clipping unit, a read-only memory that is connected to the clipping unit, a read-write memory that is connected to the clip... | 06/02/2009 |
| 7542043 | Subdividing a shader program Methods and apparatus for subdividing a shader program into regions or “phases” of instructions identifiable by phase identifiers (IDs) inserted into the shader program are provided. The phase IDs may be used to constrain execution of the shader program to prohi... | 06/02/2009 |
| 7542042 | Subpicture overlay using fragment shader A new method of operating a fragment shader to produce complex video content comprised of a video image or images, such as from a DVD player, that overlays a fragment shader-processed background. Pixels are fragment shader-processed during one loop or set of loops t... | 06/02/2009 |
| 7541835 | Circuit technique to achieve power up tristate on a memory bus Techniques and circuits for ensuring undefined control signals are not inadvertently driven onto a bus due to core logic and I/O logic supply voltages reaching final voltage levels at different times are provided. According to some embodiments, an internal voltage s... | 06/02/2009 |
| 7533237 | Off-chip memory allocation for a unified shader Systems and methods for dynamically allocating memory for thread processing may reduce memory requirements while maintaining thread processing parallelism. A memory pool is allocated to store data for processing multiple threads that does not need to be large enough... | 05/12/2009 |
| 7533236 | Off-chip out of order memory allocation for a unified shader Systems and methods for dynamically allocating memory for thread processing may reduce memory requirements while maintaining thread processing parallelism. A memory pool is allocated to store data for processing multiple threads that does not need to be large enough... | 05/12/2009 |
| 7532480 | Power delivery for electronic assemblies Embodiments of methods, apparatuses, devices, and/or systems for power delivery for electronic assemblies are disclosed. ... | 05/12/2009 |
| 7532218 | Method and apparatus for memory training concurrent with data transfer operations Embodiments of methods and apparatus for memory training concurrent with data transfers are disclosed. For an example embodiment, data may be transferred from a first memory device to a first partition of a memory controller, and a training operation may be performe... | 05/12/2009 |
| 7528843 | Dynamic texture fetch cancellation Systems and methods for dynamically canceling texture fetches may improve texture mapping performance. A shader program compiler inserts condition code writes and condition code comparison operations for shader program instructions that contribute to a texture read ... | 05/05/2009 |
| 7528839 | Faster clears for three-dimensional modeling applications A graphics processing subsystem defines a bounding area as the portion of the display buffer and other memory buffers occupied by one or more rendered objects. When clearing the memory buffers, only the portions of the buffers corresponding to the bounding area need... | 05/05/2009 |
| 7528836 | Programming multiple chips from a command buffer A CPU selectively programs one or more graphics devices by writing a control command to the command buffer that designates a subset of graphics devices to execute subsequent commands. Graphics devices not designated by the control command will ignore the subsequent ... | 05/05/2009 |
| 7526666 | Derived clock synchronization for reduced skew and jitter Two or more circuits (e.g. processing cores of a graphics processor) operate synchronously at a fast clock frequency. A core interface to each of the processing cores is designed to communicate in synchronous fashion with one or more other core interfaces at a slow ... | 04/28/2009 |
| 7526634 | Counter-based delay of dependent thread group execution Systems and methods for synchronizing processing work performed by threads, cooperative thread arrays (CTAs), or “sets” of CTAs. A central processing unit can load launch commands for a first set of CTAs and a second set of CTAs in a pushbuffer, and specify a de... | 04/28/2009 |
| 7526619 | Method for providing emulated flexible magnetic storage medium using network storage services One embodiment of the present invention sets forth a technique for emulating a floppy disk drive using network storage services. An application executing on a diskless computing device generates INT 13 access requests to gain access to a floppy disk image residing o... | 04/28/2009 |
| 7526604 | Command queueing speculative write prefetch Method and apparatus for improving system performance using controlled speculative write prefetching in systems that use command queuing. Speculative write prefetching can be forced on or off, or a determination can be made regarding the benefit versus detriment of ... | 04/28/2009 |
| 7526593 | Packet combiner for a packetized bus with dynamic holdoff time Multiple data transfer requests can be merged and transmitted as a single packet on a packetized bus such as a PCI Express (PCI-E) bus. In one embodiment, requests are combined if they are directed to contiguous address ranges in the same target device. An opportuni... | 04/28/2009 |
| 7526456 | Method of operation for parallel LCP solver A method of operating a Linear Complementarity Problem (LCP) solver is disclosed, where the LCP solver is characterized by multiple execution units operating in parallel to implement a competent computational method adapted to resolve physics-based LCPs in real-time... | 04/28/2009 |
| 7525551 | Anisotropic texture prefiltering Ripmapping and footprint assembly are used to anisotropically filter texture maps. A subset of the set of ripmaps associated with a base texture is created and stored. The subset includes ripmaps selected to maximize anisotropic texture sampling performance and to m... | 04/28/2009 |
