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| Number | Title | Issue Date |
| 7947415 | Reflective mask blank, reflective mask, method of inspecting reflective mask, and method for manufacturing the same A main object of the invention is to provide a reflective mask for EUV lithography, which may detect an alignment mark by transmission. The invention achieves the object by providing a reflective mask comprising a substrate, a multilayer formed on one side of the su... | 05/24/2011 |
| 7847585 | Source follower with active inductance as a load A semiconductor integrated circuit device comprises a transistor circuit exhibiting inductance at a desired frequency owing to capacitance between electrodes in a MOS transistor, the transistor circuit having an impedance that increases with an increase in frequency... | 12/07/2010 |
| 7846830 | Semiconductor device and method for manufacturing same The objects of the present invention is to improve the impact resistance of the semiconductor device against the impact from the top surface direction, to improve the corrosion resistance of the surface of the top layer interconnect, to inhibit the crack occurred in... | 12/07/2010 |
| 7862736 | Method of cleaning plasma etching apparatus, and thus-cleanable plasma etching apparatus Method of cleaning a plasma etching apparatus capable of suppressing variation in line width among wafers in a single lot, and improving throughput in the cleaning process, includes steps of supplying a cleaning gas into a chamber of a plasma etching apparatus; igni... | 01/04/2011 |
| 7859504 | Liquid crystal driving device, liquid crystal display device, and liquid crystal driving method A liquid crystal display device according to an embodiment of the present invention includes an active matrix type liquid crystal display panel, in which a set value of a common voltage applied to a common electrode of the liquid crystal display panel is determined ... | 12/28/2010 |
| 7853430 | Semiconductor device, and test circuit and test method for testing semiconductor device A semiconductor device includes a CDR (Clock Data Recovery) circuit and a frequency tracking control circuit. The CDR (Clock Data Recovery) circuit executes a clock data recovery on a serial data inputted synchronously with a spread spectrum clock. The frequency tra... | 12/14/2010 |
| 7844873 | Fault location estimation system, fault location estimation method, and fault location estimation program for multiple faults in logic circuit A fault location estimation system includes single-fault-assumed diagnostic unit nodes; error-observation node basis candidate classification unit; inclusion fault candidate group selection unit; inter-pattern overlapping unit; and multiple-fault simulation checking... | 11/30/2010 |
| 7843372 | D/A conversion circuit In an mode of this invention, a digital/analog conversion circuit, includes: a digital/analog conversion portion which outputs a first current according to an input digital signal; and a first current mirror circuit which generates a mirror current according to the ... | 11/30/2010 |
| 7843262 | High efficiency power amplifier Disclosed a power amplifier including a main amplifier with class bias AB and a peak amplifier with class C bias. A quarter-wave length transmission line having a length equal to one-fourth of the wave-length of a fundamental frequency is connected to an output side... | 11/30/2010 |
| 7843008 | Semiconductor device A semiconductor device capable of dissipating heat, which has been produced in an ESD protection element, to the exterior of the device rapidly and efficiently includes an ESD protection element having a drain region, a source region and a gate electrode, and a ther... | 11/30/2010 |
| 7842609 | Method for manufacturing semiconductor device A hole is formed in an insulating layer. A semiconductor substrate is heated at a temperature of equal to or more than 330° C. and equal to or less than 400° C. Tungsten-containing gas and at least one of B2H6 gas and SiH4 gas are ... | 11/30/2010 |
| 7840922 | Semiconductor design support apparatus The semiconductor design support apparatus relating to the layout verification. For executing layout verification in high accuracy, the apparatus includes a unit for generating a recognition pattern in a region having a first axis of symmetry and a second axis of sy... | 11/23/2010 |
| 7840727 | Serial-to-parallel conversion/parallel-to-serial conversion/ FIFO unified circuit Disclosed is a serial-to-parallel converter/parallel-to-serial converter/FIFO unified circuit which includes a register, a selector and a counter. The register receives serial input data and converts the serial data into parallel data based on frequency-divided mult... | 11/23/2010 |
| 7838779 | Wiring board, method for manufacturing same, and semiconductor package A wiring board in which lower-layer wiring composed of a wiring body and an etching barrier layer is formed in a concave portion formed on one face of a board-insulating film, upper-layer wiring is formed on the other face of the board-insulating film, and the upper... | 11/23/2010 |
| 7838408 | Semiconductor device, wafer and method of designing and manufacturing the same A process margin of an interconnect is to be expanded, to minimize the impact of vibration generated during a scanning motion of a scanning type exposure equipment. In a semiconductor device, the interconnect handling a greater amount of data (frequently used interc... | 11/23/2010 |
| 7836253 | Cache memory having pipeline structure and method for controlling the same A cache memory arranged between a processor and a low-speed memory and performing a pipeline processing of a memory access made by the processor. In a first stage, the cache memory reads out a tag address from a tag memory. In a second stage, the cache memory perfor... | 11/16/2010 |
| 7834669 | Semiconductor output circuit for controlling power supply to a load Between a control terminal (gate) of an output transistor of a source follower configuration and an output terminal to which a load is coupled, a depletion transistor having a relatively lower breakdown voltage (that is, smaller device-area) is provided as a shutdow... | 11/16/2010 |
| 7834461 | Semiconductor apparatus A semiconductor apparatus includes a semiconductor device formed to a first surface of a semiconductor substrate, a blocking film provided in a first via-hole, the first via-hole formed with a concave shape to the first surface of the semiconductor substrate, a firs... | 11/16/2010 |
| 7834402 | Semiconductor integrated circuit device To strengthen tolerance to radiation. Source and back gate of P-channel transistor P1 are connected to power supply. Gate of the P-channel transistor P1 is connected to input terminal IN. Gate of N1 is connected to IN. Drain of N1 is conn... | 11/16/2010 |
| 7834390 | Nonvolatile semiconductor memory device and method of manufacturing the same A nonvolatile semiconductor memory device has: a semiconductor substrate; a control gate and a floating gate that are formed side by side on a gate insulating film on a channel region in the semiconductor substrate; an erase gate facing an upper surface of the float... | 11/16/2010 |
| 7833901 | Method for manufacturing a semiconductor device having a multi-layered insulating structure of SiOCH layers and an SiOlayer In a method of manufacturing a semiconductor device where at least one insulating layer structure having a metal wiring constitution is formed to thereby construct a multi-layered wiring arrangement, a first SiOCH layer is produced. Then, a surface section of the fi... | 11/16/2010 |
| 7831939 | Semiconductor integrated circuit device featuring processed minimum circuit pattern, and design method therefor In a semiconductor integrated circuit design method for carrying out a design of circuit patterns, a plurality of circuit patterns are defined, and each of the circuit patterns is composed of at least one minimum unit area. One of the circuit patterns is selected, a... | 11/09/2010 |
| 7830740 | Semiconductor memory device having selectable transfer modes A semiconductor memory device includes a control circuit to control an access to a memory cell according to an input command, a transfer mode setting circuit to hold a transfer mode, an address pin input/output with an address in a first transfer mode and input/outp... | 11/09/2010 |
| 7830207 | Amplifier circuit A differential amplifier circuit 110 composed of an inverter is connected to the power supply voltage VCC and the ground voltage GND through a NMOS transistor 142 and a PMOS transistor 144 respectively. The NMOS transistor 142 is connecte... | 11/09/2010 |
| 7829925 | Semiconductor device and method for manufacturing same In a conventional semiconductor device, an excessive etching occurs in a section where an opening for contact plug is formed, causing a damage to a diffusion layer located under the opening. A semiconductor device 1 includes a region D1 for form... | 11/09/2010 |
| 7829439 | Laser beam processing method for making a semiconductor device In a laser beam processing apparatus that processes a semiconductor wafer having a multi-layered wiring structure formed thereon, scribe lines defined thereon, and at least one alignment mark formed on any one of the scribe lines, a laser beam generator system gener... | 11/09/2010 |
| 7829417 | Semiconductor apparatus and method of manufacturing semiconductor apparatus A semiconductor apparatus with a superjunction structure includes a gate electrode which fills a trench that is formed in an epitaxial layer, and a column region which is surrounded by the gate electrode in a plane view. A photomask for forming the column region is ... | 11/09/2010 |
| 7829246 | Method of forming pattern Formation of a constricted portion in an interconnect pattern is inhibited while moderating design rule for a phase shifting mask. When an interconnect pattern including a plurality of straight lines that are arranged in parallel is formed in a photoresist film on o... | 11/09/2010 |
| 7826492 | Communication system, cycle master node and communication method A communication system carrying out an isochronous transfer, includes a cycle master node and nodes connected with each other through a system bus. The cycle master node sets a cycle time of the isochronous transfer and transfers a cycle start packet onto the system... | 11/02/2010 |
| 7826479 | Communication message conversion device, communication method and communication system A communication message conversion device according to the present invention comprises a first receiving unit receiving a first message according to a first communication protocol, a first message storage unit storing the first message received by the first receivin... | 11/02/2010 |
| 7825673 | Failure analysis method and failure analysis apparatus Failure analysis method includes performing fixed radiation of semiconductor chip (wafer) by photocurrent generation laser beam, scanning and radiating a region to be observed on semiconductor chip by heating laser beam, detecting, by a SQUID fluxmeter, current chan... | 11/02/2010 |
| 7821823 | Semiconductor memory device, method of driving the same and method of manufacturing the same Disclosed is a semiconductor storage device comprising a semiconductor substrate, a first and a second impurity diffusion layer formed in the semiconductor substrate, a gate insulating film formed on the semiconductor substrate, and a first gate electrode formed on ... | 10/26/2010 |
| 7821817 | Semiconductor storage device In a semiconductor storage device including a transistor for reading port, undesired voltage decrease may occur in a bit line in a reading operation due to a leak current from the transistor for reading port of a memory cell, which may cause a reading error. A semic... | 10/26/2010 |
| 7821334 | Amplification circuit The present invention is aimed at realizing an amplifying circuit whose chip size is prevented from being significantly increased even if the number of compatible frequencies increases, and which has a wide dynamic range when it operates under a low voltage. The amp... | 10/26/2010 |
| 7821115 | Tape carrier package including a heat dissipation element A semiconductor device on a tape carrier package with improved heat dissipation, as provided. The number of outputs of the semiconductor device has been increased for implementing a multi-channel configuration, and narrower pitches are employed. Included are a tape ... | 10/26/2010 |
| 7821037 | Heterojunction bipolar transistor A heterojunction bipolar transistor includes a first conductivity type subcollector layer, a first collector layer containing a first conductivity type impurity, a third collector layer containing a higher concentration of the first conductivity type impurity than t... | 10/26/2010 |
| 7820489 | Method of manufacturing semiconductor apparatus A method of manufacturing a semiconductor apparatus includes forming an electrode on a semiconductor device, forming a conductive bump on the electrode, placing an external wire on the conductive bump, and laser-welding the external wire and the conductive bump to e... | 10/26/2010 |
| 7819723 | Retainer ring and polishing machine To provide a retainer ring by which an object to be polished can be uniformly polished, and deterioration thereof can be suppressed, and it does not take time to recycle, and a polishing machine having the retainer ring. The retainer ring 1 includes: a first ... | 10/26/2010 |
| 7818706 | Semiconductor integrated circuit device Disclosed is a semiconductor integrated circuit device operated in stability by high-speed clock signals and which is high in a cell using rate and in interconnection efficiency. In a mid part of a chip, there are provided an I/O 11b, supplied with a c... | 10/19/2010 |
| 7818598 | Semiconductor device A semiconductor device provided on a semiconductor substrate having a cell placing area disposed on a semiconductor substrate, the cell placing area including a plurality of basic cells supplied with power from a local power supply line, a global power supply line t... | 10/19/2010 |
