Assignee: NEC Electronics Corp.

Location: JP
No. of patents: 4

Number	Title	Issue Date
7498249	Method of forming a connecting conductor and wirings of a semiconductor chip A resist post is formed on a connection pad of a semiconductor chip, and the semiconductor chip and the resist post are covered by a heat resistant insulating layer. A surface of the insulating layer is next polished by CMP or the like, thus an upper surface of the ...	03/03/2009
7360116	Built-in self test circuit A built-in self test circuit (BIST circuit) in an LSI includes a verification test pattern generator for generating verification test pattern which is used for verifying the connections in the LSI including the BIST circuit in the design stage thereof, and another t...	04/15/2008
6778213	Active X-Y addressable type solid-state image sensor and method of operating the same There is provided a solid-state image sensor including a photoelectric transfer section and a CMOS circuit section both formed on a common semiconductor substrate in accordance with a common process, the solid-state image sensor outputting a signal indicative of a v...	08/17/2004
6589863	Semiconductor device and manufacturing method thereof There is presented a structure in which outlines of a metal interconnection 111 that is laid in an interlayer insulating film are covered with a barrier metal film 110. As the material for the barrier metal film 110, TaN or the like is utilized....	07/08/2003

PatentStorm