Did You Know...
...that the Eveready Battery began as an invention called the "electric flowerpot," which was a tube with a battery and light bulb inside? The idea was to fasten this gizmo to the side of a flowerpot so it would illuminate the flowers from the bottom. The idea died on the vine and the businessman who licensed the flower pot, Conrad Huber, was left with a pile of useless tubes -- until he found a way to market them as batteries to light the world!
PatentStorm News
Make the Most of Our Site
See this month's Top Inventors and Most Cited Patents.
Stay on top of the latest innovations by subscribing to an RSS feed.
Registered users: Manage your profile.
| Number | Title | Issue Date |
| 4599118 | Method of making MOSFET by multiple implantations followed by a diffusion step A short channel metal oxide semiconductor transistor device is processed without undesirable short channel effects, such as VT falloff and with a reasonable source-drain operating voltage support. In a substrate lightly doped with P-type conduc... | 07/08/1986 |
| 4595845 | Non-overlapping clock CMOS circuit with two threshold voltages A set of clock-controlled CMOS logic circuits employ a single pair of non-overlapping clocks controlling a set of transmission gates that have only a single pass transistor and a compensating non-standard threshold voltage in a portion of the logic gates.... | 06/17/1986 |
| 4580067 | MOS dynamic load circuit for switching high voltages and adapted for use with high threshold transistors A dynamic load circuit (34) selectively applies a high voltage state to a circuit node (42). A clock signal is coupled to a first node (54) and the inverse of the clock signal is coupled to a second node (60). Isolation transistors (50, 70) are controlled... | 04/01/1986 |
| 4573146 | Testing and evaluation of a semiconductor memory containing redundant memory elements A method and apparatus is described for initiating a selected functional mode for a semiconductor memory circuit to determine the implementation of redundant elements in a semiconductor memory. The method for initiating the selected functional mode compri... | 02/25/1986 |
| 4571708 | CMOS ROM Data select circuit A data select circuit for selecting a column line in a CMOS ROM and for establishing a connection between a pair of bit lines and corresponding data lines uses a single NMOS pull-down transistor on the column line and a pair of P-channel pass transistors ... | 02/18/1986 |
| 4567389 | CMOS Differential amplifier A differential sense amplifier employs a central region having two current paths each having a P- and N-type transistor in series, all four transistors having a common gate connection. Each input transistor has its source connected to the top of one curre... | 01/28/1986 |
| 4564920 | Multiplier with hybrid register An integrated-circuit CPU saves layout space by employing the Address Register as the Extension Register for multiplication operations, the Address Register being modified to include shifting hardware.... | 01/14/1986 |
| 4553314 | Method for making a semiconductor device A method for making a semiconductor device is described in which overlapping polycrystalline silicon layers are deposited over selected portions of a semiconductor substrate and insulated from the substrate and from each other, thereby providing an improv... | 11/19/1985 |
| 4549336 | Method of making MOS read only memory by specified double implantation The power consumption and corresponding speed of an integrated circuit is scaled by means of adjusting the channel width for MOS transistors. A transistor (12) is initially fabricated with a channel (24) having a width W1. The channel (24) rece... | 10/29/1985 |
| 4545035 | Dynamic RAM with nonvolatile shadow memory A compact memory cell combines a volatile dynamic storage section with a shadow nonvolatile section in two vertically stacked element arrays.... | 10/01/1985 |
| 4545036 | Sense amplifier with time dependent sensitivity A dynamic RAM integrated circuit has improved resistance to soft errors caused by alpha particles by changing the trip-point voltage of the sense amplifier from a first value that provides resistance to bit line errors to a second, lower value that provid... | 10/01/1985 |
| 4535427 | Control of serial memory A FIFO memory chip includes read and write pointers in the form of an X and a Y shift register carrying a pair of pointer bits that point to a memory cell in a rectangular cell array.... | 08/13/1985 |
| 4527258 | E2 PROM having bulk storage An electrically erasable programmable read only memory employs a single unsteered on-chip high voltage generator that applies high voltage simultaneously to all cells on the chip.... | 07/02/1985 |
| 4523110 | MOSFET sense amplifier circuit A MOSFET sense amplifier applies both input signals to both input transistors of a common-gate sense amplifier; each input signal being applied to the source of one input transistor and the gate of the other, thereby effectively doubling the applied input... | 06/11/1985 |
| 4521698 | Mos output driver circuit avoiding hot-electron effects An output driver circuit for a Mos integrated circuit eliminates the problem of charge injection into the substrate by employing a switching circuit responsive to the voltage on the output node to control the voltage drop on the output transistor.... | 06/04/1985 |
| 4510584 | MOS Random access memory cell with nonvolatile storage A nonvolatile random access memory cell (10) includes a static random access memory circuit and a corresponding nonvolatile memory circuit. The volatile memory circuit operates in a conventional manner and has first and second data states. Upon receipt of... | 04/09/1985 |
| 4508815 | Recessed metallization An improved method of planarizing a level of metallization employs a trench in a smooth-surfaced dielectric and a sequence of etching steps to cut the trench locally down to the substrate, while forming the main metallization pattern at the same time.... | 04/02/1985 |
| 4507538 | Laser hardening with selective shielding A method of surface hardening a metal corner includes the application of a laser beam to the surface, a portion of the beam being blocked by a cooled tube, so that the corner is heated by conduction from the heated areas.... | 03/26/1985 |
| 4507761 | Functional command for semiconductor memory A method and apparatus is described for initiating a selected functional mode for a semiconductor memory circuit. The method for initiating the selected functional mode comprises applying an active state of at least a first of the operational signals to t... | 03/26/1985 |
| 4506347 | Placement of clock circuits for semiconductor memory A dynamic random access memory (10) is fabricated on a substrate (12) and is divided into memory sections (14, 16). Memory cells (46) are connected to bit lines (18-28, a and b), which are organized into pairs that are connected to respective sense amplif... | 03/19/1985 |
| 4502140 | GO/NO GO margin test circuit for semiconductor memory A semiconductor memory circuit (140) includes a plurality of memory cells each having an access transistor (154, 158) and a storage capacitor (162, 166). The memory cells are connected to digit lines (142, 144) each of which is split into halves each conn... | 02/26/1985 |
| 4499652 | Method of forming a MOSFET with both improved breakdown resistance and less hot-electron effects A field effect transistor has improved punch-through resistance by the implantation of a dose of ions through the center of the active area. The energy of the dose is such that the ion concentration peaks at the depth most susceptible to punch-through. Th... | 02/19/1985 |
| 4495602 | Multi-bit read only memory circuit A read only memory circuit (10) includes an array of memory transistors including a row of such transistors (12-28) connected to a common word line (30). For each column of memory transistors there is provided a set of reference transistors which receive ... | 01/22/1985 |
| 4492927 | Offset voltage compensation circuit A dual-tone multi-frequency (DTMF) tone generator circuit (10) produces selected frequency row and column tones which are combined to generate a DTMF signal. Key board scan circuits (42, 44) scan a conventional push-button telephone key board to produce r... | 01/08/1985 |
| 4491936 | Dynamic random access memory cell with increased signal margin A dynamic random access memory cell (30) includes an access transistor (32) having the gate terminal thereof connected to a word line (34) and the source and drain terminals thereof connected between a bit line (36) and a node (37). A charge storage capac... | 01/01/1985 |
| 4490812 | User reprogrammable programmed logic array A user-programmable and reprogrammable programmed logic array includes a self-indexing pointer to direct successive input signals to the proper cell within the array. A particular application is that of a ROM patch to correct coding errors in a ROM.... | 12/25/1984 |
| 4479097 | Low voltage, low power RC oscillator circuit A resistor-capacitor oscillator circuit (10) is provided and includes a voltage comparator circuit (12). A capacitor (20) is connected to an input terminal (14) of the voltage comparator circuit (12). A resistor divider network (30) is coupled to an input... | 10/23/1984 |
| 4477739 | MOSFET Random access memory chip A dynamic random access read/write memory having 4,096 binary storage cells is disclosed. The system utilizes a single set of six address input buffers and one decoder for both row and column address information. The memory array includes two 32×64 array... | 10/16/1984 |
| 4472871 | Method of making a plurality of MOSFETs having different threshold voltages An integrated circuit using MOSFETs having varying threshold voltages permitting improved performance and reduced area utilization on a monolithic semiconductor chip is produced by selectively varying ion implantation doses in the channels of the MOSFETs.... | 09/25/1984 |
| 4472678 | Test apparatus for circuits having a multiplex input/output terminal including a load connected to the terminal together with circuitry for monitoring the current flow through the load when inputting a signal to the terminal A test circuit (10) provides high and low reference voltages to a circuit (92) under test. A load (52) is connected to a multiplexed terminal (90) of circuit (92). A current source transistor (48) and a current sink transistor (132) are connected to provi... | 09/18/1984 |
| 4472644 | Bootstrapped clock driver including delay means A clock generator circuit (10) receives an input signal PPC.0. and generates a delayed clock output signal PC.0.. The circuit (10) is set to an initial condition by a precharge signal PC.0.R prior to a transition of the input signal PPC.0.. A time delay s... | 09/18/1984 |
| 4460978 | Nonvolatile static random access memory cell A nonvolatile static random access memory cell (10) includes a pair of cross-coupled transistors (12, 14) which function as a bistable circuit to store data states. Variable threshold transistors (36, 41) are respectively connected in series between the d... | 07/17/1984 |
| 4458212 | Compensated amplifier having pole zero tracking A circuit for producing a compensated output signal includes a first and second stage of amplification (18) and (20) and a compensation circuit (16). The first stage of amplification (18) has a signal input, a signal output and a control input. The second... | 07/03/1984 |
| 4453037 | Loop length compensation circuit A compensation circuit (10) controls the gain of transmit and receive amplifiers (47), (49) as a function of a residual input current (Ires). Circuit (10) includes a constant current source (24) which is connected to produce mirrored constant c... | 06/05/1984 |
| 4451885 | Bit operation method and circuit for microcomputer A microcomputer circuit is described for carrying out bit operations between registers and ports without the need for bit testing followed by branch operations. The microcomputer includes a bus (10) connected to provide communication to an ALU (22), regis... | 05/29/1984 |
| 4451742 | Power supply control for integrated circuit A power supply control circuit (20) selectively provides power to an integrated circuit from either a primary power supply terminal (22), or through terminals (24, 26) connected to backup batteries. The voltage level of the primary power is monitored cont... | 05/29/1984 |
| 4446436 | Circuit for generating analog signals A tone synthesizer circuit (10) includes a multi-tap resistor (86) which produces a plurality of discrete voltages at the taps (T1-T16). A switch (88-118) is provided for each of the taps (T1-T16). The tap switches (88-118) are organized into four groups.... | 05/01/1984 |
| 4445266 | MOSFET Fabrication process for reducing overlap capacitance and lowering interconnect impedance A method of forming a plurality of interconnected metal oxide semiconductor field effect transistors on P-type semiconductor substrate (10). A layer of oxide (14) is formed on the substrate (10) and then a polysilicon layer (16) is formed on top of the ox... | 05/01/1984 |
| 4445002 | Sidetone circuit A sidetone circuit (44) is connected to the terminals of a two-line telephone system. The sidetone circuit (44) receives inputs from a DTMF source (62) and a microphone (72). These inputs are selectively passed through a circuit (82) to produce a modulati... | 04/24/1984 |
| 4441119 | Integrated circuit package An improved integrated circuit package (10) includes a cover (12), an intermediate subassembly (14) and a bottom subassembly (16). The intermediate and bottom subassemblies (14, 16) include lead frames (48, 22) respectively embedded therein, as well as op... | 04/03/1984 |
