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| Number | Title | Issue Date |
| 7592240 | Method for forming a gate structure through an amorphous silicon layer and applications thereof A fabrication method for forming a gate structure through an amorphous silicon layer includes providing a substrate layer, forming an amorphous silicon layer of a selected thickness on the substrate layer at a reaction temperature between about 520° C. and 560° C.... | 09/22/2009 |
| 7432204 | Wafer and the manufacturing and reclaiming methods thereof A wafer and the manufacturing and reclaiming methods thereof are disclosed. The wafer includes a semiconductor substrate and a protective layer formed on the surface of the semiconductor substrate. The reclaiming method of the wafer includes providing a wafer having... | 10/07/2008 |
| 7402522 | Hard mask structure for deep trenched super-junction device A hard mask structure is disclosed. The hard mask structure is used for manufacturing a deep trench of a super-junction device having a substrate and an epitaxial layer formed on the substrate. The hard mask structure comprises an ion barrier layer formed on the epi... | 07/22/2008 |
| 7375005 | Method for reclaiming and reusing wafers Embodiments of the present invention provide a method for reclaiming and reusing a wafer. In one embodiment, a method for reclaiming a wafer comprises providing a used, nonproductive wafer having a semiconductor substrate and a polysilicon layer formed on the semico... | 05/20/2008 |
| 7358168 | Ion implantation method for forming a shallow junction A shallow junction that previously would require the use of a low-energy ion implanter can be directly formed by high-energy or middle-energy ion implanters such that the manufacturer need not purchase a new low-energy ion implanter. In one embodiment, an ion-implan... | 04/15/2008 |
| 7344998 | Wafer recovering method, wafer, and fabrication method In order to use an etching solution of less complicated composition for recovering used wafers, embodiments of the present invention provide a recovering method, and also provide a kind of wafer, which is used as a process control wafer or dummy wafer, and fabricati... | 03/18/2008 |
| 7282429 | Method of manufacturing Schottky diode device Embodiments of the invention provide a method of manufacturing a Schottky diode device. In one embodiment, the method includes: (a) providing a substrate; (b) sequentially forming a gate oxide layer and a polysilicon layer on the substrate; (c) partially oxidizing t... | 10/16/2007 |
| 7271048 | Method for manufacturing trench MOSFET A method of manufacturing a trench MOSFET with high cell density is disclosed. The method introduces a sidewall oxide spacer for narrowing the opening of the trench structure, thereby decreasing the cell pitch of the memory units. Moreover, the source structure is f... | 09/18/2007 |
| 7265024 | DMOS device having a trenched bus structure A DMOS device having a trench bus structure thereof is introduced. The trench bus structure comprises a field oxide layer formed on a P substrate, and a trench extending from an top surface of the field oxide layer down to a lower portion of the P substrate. A gate ... | 09/04/2007 |
| 7211523 | Method for forming field oxide A method for forming a field oxide is disclosed. In one embodiment, the method comprises providing a semiconductor structure having a substrate, a pad oxide, and a patterned barrier layer, performing a dry oxidation process to form a first field oxide on the substra... | 05/01/2007 |
| 7205196 | Manufacturing process and structure of integrated circuit The present invention provides a manufacturing process and the structure of an integrated circuit. In one embodiment, one polysilicon layer deposition and one polysilicon layer etching are used to form the gate of a trench device and the polysilicon layer of a plana... | 04/17/2007 |
| 7192789 | Method for monitoring an ion implanter A method for monitoring an ion implanter is disclosed. In one embodiment, the method comprises providing a wafer, forming a barrier layer on the surface of the wafer wherein the barrier layer has a substantial blocking effect on ion implantation, performing an ion i... | 03/20/2007 |
| 7118971 | Method for fabricating trench power device Embodiments of the invention relate to a fabrication method of an electronic device, more particularly to a fabrication method of a power device in which an oxide layer at the bottom of the trench is provided to reduce Miller capacitance and further reduce RC delay.... | 10/10/2006 |
| 7118778 | Method of applying adhesive An applying method for an adhesive according to an embodiment includes the following steps. First, gas is exhausted from a first exhaust pipe, so as to eliminate a part of the gas in a closed container. Next, the gas continues to be exhausted from the first exhaust ... | 10/10/2006 |
| 7092836 | Method for locating wiring swap in a hi-fix structure of a simultaneous multi-electronic device test system A method for locating wiring swap in a hi-fix structure of a simultaneous multi-electronic device test system is introduced to screen the complicated wiring state of the hi-fix structure and to pinpoint the wiring swap thereinside as well. The hi-fix structure has a... | 08/15/2006 |
| 7087958 | Termination structure of DMOS device In one embodiment of the invention, a semiconductor device set includes at least one trench-typed MOSFET and a trench-typed termination structure. The trench-typed MOSFET has a trench profile and includes a gate oxide layer in the trench profile, and a polysilicon l... | 08/08/2006 |
| 7084457 | DMOS device having a trenched bus structure A DMOS device having a trench bus structure thereof is introduced. The trench bus structure comprises a field oxide layer formed on a P substrate, and a trench extending from an top surface of the field oxide layer down to a lower portion of the P substrate. A gate ... | 08/01/2006 |
| 7047620 | Method for assembling a scrubber The present invention relates to a method of assembling a scrubber which includes a motor, a shaft rotatably coupled to and extending through the motor, a shaft pin detachably connected to the shaft, and a disk coupled to the shaft and having a notch located relativ... | 05/23/2006 |
| 7015112 | Method of forming bottom oxide layer in trench structure Embodiments of the invention are directed to a method of forming a bottom oxide in a trench structure. In one embodiment, the method includes steps of providing a semiconductor substrate and forming a trench structure in the semiconductor substrate; performing an PE... | 03/21/2006 |
| 7004012 | Method of estimating thickness of oxide layer Embodiments of the present invention are directed to providing a leakage detecting method for use in an oxidizing system of forming an oxide layer so as to shorten leakage detecting time period. In one embodiment, a leakage detecting method for use in an oxidizing s... | 02/28/2006 |
| 6998315 | Termination structure for trench DMOS device and method of making the same Embodiments of the present invention are directed to a termination structure provided for a trench DMOS device to reduce occurrence of current leakage resulting from electric field crowding at the border of the active area and a method of manufacturing the same. In ... | 02/14/2006 |
| 6991994 | Method of forming rounded corner in trench A method for forming a trench having rounded corners in a semiconductor device comprises providing a substrate; forming a first pad oxide layer, a first silicon nitride layer, and a first oxide layer on the substrate sequentially; removing portions of the first oxid... | 01/31/2006 |
| 6989306 | Termination structure of DMOS device and method of forming the same Embodiments of the invention provide a termination structure of DMOS device and a method of forming the same. In forming the termination structure, a silicon substrate with an epitaxial layer formed thereon is provided. A body region defined by doping the epitaxial ... | 01/24/2006 |
| 6974749 | Bottom oxide formation process for preventing formation of voids in trench Embodiments of the present invention are directed to a method of forming a bottom oxide layer in the trench in semiconductor devices, such as Double-Diffused Metal-Oxide Semiconductor (DMOS) devices. In one embodiment, a method of forming a bottom oxide layer in a t... | 12/13/2005 |
| 6958276 | Method of manufacturing trench-type MOSFET In a method of manufacturing MOSFET devices, and particularly to the trench-type MOSFET devices, embodiments of the present invention provide methods of forming bottom oxide layers having uniform thickness on the bottom of the trenches and avoiding undesired damage ... | 10/25/2005 |
| 6916126 | Developing method for semiconductor substrate Embodiments of the present invention provide a developing method, which can efficiently prevent the developing solution from remaining on the backside surface of the wafer, so as to avoid the influence of the contamination on the subsequent processes. In one embodim... | 07/12/2005 |
| 6888197 | Power metal oxide semiconductor field effect transistor layout A power MOSFET layout according to one embodiment of the invention comprises a substrate and a plurality of cells. Each of the cells includes a base portion, a plurality of protruding portions extending from the base portion, and a plurality of photo-resist regions.... | 05/03/2005 |
| 6880382 | Leakage detecting method for use in oxidizing system of forming oxide layer Embodiments of the present invention are directed to providing a leakage detecting method for use in an oxidizing system of forming an oxide layer so as to shorten leakage detecting time period. In one embodiment, a leakage detecting method for use in an oxidizing s... | 04/19/2005 |
| 6875085 | Polishing system including a hydrostatic fluid bearing support A polishing system such as a chemical mechanical belt polisher includes a hydrostatic fluid bearing that supports polishing pads and incorporates one or more of the following novel aspects. One aspect uses compliant surfaces surrounding fluid inlets in an array of i... | 04/05/2005 |
| 6859754 | Statistical process control method and system thereof A statistical process control (SPC) method, wherein a post-stage process corresponds to a pre-stage process, is disclosed in the present invention. In one embodiment, the SPC method comprises: collecting a plurality of pre-stage measurements and post-stage measureme... | 02/22/2005 |
| 6855986 | Termination structure for trench DMOS device and method of making the same Embodiments of the present invention are directed to a termination structure provided for a trench DMOS device to reduce occurrence of current leakage resulting from electric field crowding at the border of the active area and a method of manufacturing the same. In ... | 02/15/2005 |
| 6828196 | Trench filling process for preventing formation of voids in trench Embodiments of the present invention relate to a process for filling a trench structure of a semiconductor device to prevent formation of voids in the trench structure so as to minimize current leakage and provide excellent electrical properties. In one embodiment, ... | 12/07/2004 |
| 6826822 | Method for preparing rubber plate used in an ion implanter One embodiment is directed to a method for trimming a rubber plate which is configured to be placed on a platform of an ion implanter, wherein the platform of the ion implanter includes a plurality of primary holes and a plurality of primary notches. The method comp... | 12/07/2004 |
| 6821913 | Method for forming dual oxide layers at bottom of trench Embodiments of the present invention are directed to an improved method for forming dual oxide layers at the bottom of a trench of a substrate. A substrate has a trench which includes a bottom and a sidewall. The trench may be created by forming a mask oxide layer o... | 11/23/2004 |
| 6812148 | Preventing gate oxice thinning effect in a recess LOCOS process Embodiments of the present invention relate to a method for preventing gate oxide thinning in a recess LOCOS process. The plurality of trenches are separated by a patterned pad oxide and a patterned silicon nitride layer The patterned silicon nitride layer and the p... | 11/02/2004 |
| 6784115 | Method of simultaneously implementing differential gate oxide thickness using fluorine bearing impurities Improved methods for fabricating semiconductor integrated circuit devices, in particular flash EEPROM devices. According to an embodiment, the present invention provides a method of forming a semiconductor device having a gate oxide layer (160) that is thin i... | 08/31/2004 |
| 6758940 | Apparatus and method for controlling boiling conditions of hot phosphoric acid solution with pressure adjustment Disclosed is an apparatus and method for controlling boiling condition of hot H3PO4 solution by adjusting the vapor extracting rate thereof, wherein an acid tank filled with hot H3PO4 solution to a level surface is located... | 07/06/2004 |
| 6756168 | Determining exposure time of wafer photolithography process Embodiments of the present invention relate to a method and a system for determining an exposure time of a wafer photolithography process is applied to a wafer photolithography system and is used to determine the preferred exposure time for the L(N) batch production... | 06/29/2004 |
| 6743075 | Method for determining chemical mechanical polishing time The present invention relates to a method for determining rapidly and accurately the polishing time of a chemical mechanical polishing process for polishing target wafers to avoid any problems of under-polishing or over-polishing. An aspect of the present invention ... | 06/01/2004 |
| 6741520 | Integrated data input sorting and timing circuit for double data rate (DDR) dynamic random access memory (DRAM) devices An integrated data input sorting and timing circuit for double data rate (“DDR”) dynamic random access memory (“DRAM”) devices in which a sorting of the input data into odd/even is integrated with the necessary timing to allow synchronization with the on-chi... | 05/25/2004 |
