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| Number | Title | Issue Date |
| 6875287 | Water reclamation rate in semiconductor fabrication wet benches Embodiments of the present invention are directed to improving the reclamation rate of the waste water of wet benches in semiconductor fabrication. In accordance with an aspect of the invention, a method for improvement of water reclamation rate comprises choosing a... | 04/05/2005 |
| 6740571 | Method of etching a dielectric material in the presence of polysilicon A method is provided for advantageously etching dielectric material between highly integrated polysilicon devices with high dielectric-to-polysilicon selectivity to expose polysilicon with minimal polysilicon loss and without photoresist lift. A wet etch solution co... | 05/25/2004 |
| 6562681 | Nonvolatile memories with floating gate spacers, and methods of fabrication In a nonvolatile memory, a floating gate includes a portion of a conductive layer (150), and also includes conductive spacers (610). The spacers increase the capacitive coupling between the floating gate and the control gate (170).... | 05/13/2003 |
| 6559055 | Dummy structures that protect circuit elements during polishing Circuit elements (e.g. transistor gates) formed over a semiconductor substrate are protected by adjacent dummy structures during mechanical or chemical mechanical polishing of an overlying dielectric.... | 05/06/2003 |
| 6544847 | Single poly non-volatile memory structure and its fabricating method The present invention discloses a method for fabricating a non-volatile memory structure from a single layer of polysilicon in a semiconductor substrate, wherein the semiconductor substrate with two active areas, first and second, are divided by isolation... | 04/08/2003 |
| 6531387 | Polishing of conductive layers in fabrication of integrated circuits In fabrication of integrated circuits, trenches (184) are formed in a dielectric (170), then a metal (e.g. tungsten or copper) is deposited. The metal (194) is removed from the top surface of the dielectric by a polishing process (e.g. CMP). The metal rem... | 03/11/2003 |
| 6500712 | Fabrication of dielectric in trenches formed in a semiconductor substrate for a nonvolatile memory To form substrate isolation for a nonvolatile memory, floating gate polysilicon (410) is formed over a semiconductor substrate (110), then silicon nitride (130) is deposited, and then the nitride, the floating gate polysilicon and the substrate are etched... | 12/31/2002 |
| 6465369 | Method for stabilizing semiconductor degas temperature A method for stabilizing a degas temperature of wafers in a degas chamber comprises (a) setting an electrical heater at an initial output power, (b) heating each wafer for a first period of time to keep the temperature of the wafer at a predetermined rang... | 10/15/2002 |
| 6423611 | Manufacturing process of capacitor A method for manufacturing a capacitor includes the steps of a) forming a sacrificial layer over the etching stop layer, b) partially removing the sacrificial layer, the etching stop layer, and the dielectric layer to form a contact window, c) forming a f... | 07/23/2002 |
| 6406953 | Method for fabricating an integrated circuit with a transistor electrode Dynamic Random Access Memory (DRAM) cells are formed in a P well formed in a biased deep N well (DNW). PMOS transistors are formed in N wells. The NMOS channels stop implant mask is modified not to be a reverse of the N well mask in order-to block the cha... | 06/18/2002 |
| 6399980 | Fabrication of a T-shaped capacitor A method for manufacturing a capacitor includes the steps of a) forming a sacrificial layer over the etching stop layer, b) partially removing the sacrificial layer, the etching stop layer, and the dielectric layer to form a contact window, c) forming a f... | 06/04/2002 |
| 6386213 | Plate-tilting apparatus A plate-tilting apparatus adapted to be used in a semiconductor-manufacturing process is disclosed. The plate-tilting apparatus is used for preventing thin wafers from being collected in a cassette contacted with each other after the thin wafers are taken... | 05/14/2002 |
| 6388265 | Method for distinguishing a specific region in a sample to be observed by a microscope A method for distinguishing a specific region in a sample to be observed by a microscope is disclosed. The method includes the steps of (a) forming a first concavity on a first side of the specific region by a focus ion beam (FIB) technique, (b) forming a... | 05/14/2002 |
| 6384482 | Method for forming a dielectric layer in a semiconductor device by using etch stop layers The invention provides a method for forming a dielectric layer in a semiconductor device by using etch stop layers, and a semiconductor structure formed by the method. The method in accordance with the invention comprises: providing a semiconductor substr... | 05/07/2002 |
| 6380072 | Metallizing process of semiconductor industry A method for manufacturing a semiconductor device having an excellent metallization is provided. The method includes the steps of a). providing a semiconductor substrate, b) forming a conductive layer on the semiconductor substrate, c) forming a dielectri... | 04/30/2002 |
| 6376300 | Process of manufacturing trench capacitor having a hill structure A process of manufacturing a trench capacitor having a hill structure includes the steps of providing a semiconductor substrate, forming a passivation layer on the semiconductor substrate, etching the passivation layer to form a trench defined by a side w... | 04/23/2002 |
| 6374833 | Method of in situ reactive gas plasma treatment A method of in situ reactive gas plasma treatment is disclosed. The method is capable of removing a residue remained in a metal etching chamber after the metal etching process to improve the yield of the wafer and the particle performance of the metal etc... | 04/23/2002 |
| 6358676 | Method for reworking photoresist An improved method for reworking photoresist is provided for decreasing cycle time of photoresist reworking process. A semiconductor substrate with an underlying layer is provided for patterning. A photoresist pattern is formed on the underlying layer. A ... | 03/19/2002 |
| 6346418 | Method for evaluation of metal impurity in lithographic materials A method for evaluating ratios of metallic impurities in lithographic materials is disclosed. The method comprises: separating said metal from said lithographic material by microwave heating; then adding said metal to an acid to form a solution; and final... | 02/12/2002 |
| 6334258 | Inspection device for examining a piece of aperture graphite of an extraction electrode An inspection device for examining a piece of aperture graphite of an extraction electrode, and the aperture graphite includes a to-be-examined curve and a to-be-examined engagement portion. The inspection device includes a sidewall surface having a stand... | 01/01/2002 |
| 6326320 | Method for forming oxide layer on conductor plug of trench structure A method for forming oxide layer on conductor plug of trench structure is proposed. The invention includes following essential steps: First, provide a substrate where a trench locates inside the substrate, herein the trench is partly filled by a conductor... | 12/04/2001 |
| 6326574 | Sleeve for an adapter flange of the gasonics L3510 etcher A sleeve means is described. The sleeve means comprises a round plane and ring-shaped side adjacent to the round plane. The round plane has a central hole and six periphery holes thereon. The central hole and six peripheral holes respectively correspond t... | 12/04/2001 |
| 6303436 | Method for fabricating a type of trench mask ROM cell A method for fabricating a type of Trench Mask ROM cell comprises steps including: providing a substrate doped lightly with p-type dopant, sequentially forming a pad oxide layer and a nitride layer on the substrate; etching back the pad oxide layer, the n... | 10/16/2001 |
| 6266290 | Programmable latches that include non-volatile programmable elements A non-volatile programmable latch (210) has a fuse (F1) connected between a non-ground voltage terminal (212) and an output terminal (OUT). A NMOS transistor (110) is connected between the output terminal and ground. An inverter (120) has an input connect... | 07/24/2001 |
| 6261893 | Method for forming a magnetic layer of magnetic random access memory The present invention relates to a method for forming a magnetic layer of magnetic random access memory. In short, the method comprises following steps: providing a substrate; forming metal structures on substrate; forming a stop layer on substrate and mo... | 07/17/2001 |
| 6251722 | Method of fabricating a trench capacitor A method of fabricating a trench capacitor having high capacitance for ULSI technology below the sub-micrometer scale is provided. The method includes: form a trench on a semiconductor substrate. The trench has a bottom portion and at least one sidewall o... | 06/26/2001 |
| 6235604 | Manufacturing process for a capacitor A method for manufacturing a capacitor includes the steps of a) forming a sacrificial layer over the etching stop layer, b) partially removing the sacrificial layer, the etching stop layer, and the dielectric layer to form a contact window, c) forming a f... | 05/22/2001 |
| 6228729 | MOS transistors having raised source and drain and interconnects A process for fabricating a semiconductor device comprising a gate electrode, a raised source, a raised drain and an interconnect inlaid into an isolation region. A semiconductor device is fabricated by a process comprising the following steps: forming se... | 05/08/2001 |
| 6228776 | Ashing process by adjusting etching endpoint and orderly stepped positioning silicon wafer A method used in some step of processing for ashing a photoresist resin film of a semiconductor wafer is disclosed. Generally the present method will conclude the following steps. Firstly adjusting Etch-Module-Asher endpoint is carried out. Then placing t... | 05/08/2001 |
| 6218275 | Process for forming self-aligned contact of semiconductor device A process for forming a contact structure of a semiconductor device includes the steps of (a) providing a substrate having a plurality of gates thereon and a first oxide layer formed between the gates, (b) forming a first dielectric layer on the oxide lay... | 04/17/2001 |
| 6191997 | Memory burst operations in which address count bits are used as column address bits for one, but not both, of the odd and even columns selected in parallel. In a burst operation, a counter (18) receives one or more bits of a starting column address. The count signal (A[2:1]) generated by the counter is provided to an address adder (20). The address adder generates column address bits (B[2:1]) for a column to ... | 02/20/2001 |
| 6185159 | Radio control alarm device An alarm device for ringing an alarm at a variable time comprises a receiver, a processor and a speaker. The receiver receives a radio frequency signal carrying a standard time and an alarm time correction and transfers the standard time and the alarm tim... | 02/06/2001 |
| 6180980 | Trench non-volatile memory cell A method of manufacturing a trench non-volatile memory cell, comprises the steps of: providing a semiconductor substrate; performing ion implantation to form a source region in the semiconductor substrate; forming a trench on the semiconductor substrate b... | 01/30/2001 |
| 6153462 | Manufacturing process and structure of capacitor A method is provided for manufacturing a capacitor having a generally crosssectionally modified T-shaped structure with a rough surface to serve as a lower capacitor plate, and having another dielectric layer and another conducting layer to construct an u... | 11/28/2000 |
| 6153907 | IC layout structure for MOSFET having narrow and short channel A specific IC layout structure for the MOSFET having a narrow and short channel, especially when the width and the length of the channel are both as small as 1 micron or less, is disclosed. In the IC layout structure, a mask includes a first mask region f... | 11/28/2000 |
| 6150244 | Method for fabricating MOS transistor having raised source and drain A process for fabricating a semiconductor device comprising a raised source and drain. A semiconductor device is fabricated by a process comprising the following steps: forming active regions separated by isolation regions; forming at each active region a... | 11/21/2000 |
| 6150238 | Method for fabricating a trench isolation A method for fabricating a trench isolation is disclosed. First, a first insulated layer having a void is formed within the trench of the semiconductor. Next, the upper portion of said first insulated layer is etched to remove the void of said first insul... | 11/21/2000 |
| 6144059 | Process and structure for increasing capacitance of stack capacitor The present invention provides a process and a structure for increasing a capacitance of a stack capacitor. The process includes steps of: a) forming a contact hole on a silicon substrate having an oxide layer, b) forming a polysilicon contact plug of a f... | 11/07/2000 |
| 6127699 | Method for fabricating MOSFET having increased effective gate length A process for fabricating a semiconductor device comprising a source, a drain, and a gate electrode having an increased effective gate length. A semiconductor device is fabricated by a process comprising the following steps: forming active areas separated... | 10/03/2000 |
| 6123865 | Method for improving etch uniformity during a wet etching process A method for improving etch uniformity during a wet etching process is disclosed. The method comprises the steps of first rinsing the wafer to form a water film over the wafer surface, followed by liquid phase etching. The water film helps the subsequent ... | 09/26/2000 |
