Assignee: Mips Technologies, Inc.

Location: Mountain View, CA
No. of patents: 78

Number	Title	Issue Date
8145884	Apparatus, method and instruction for initiation of concurrent instruction streams in a multithreading microprocessor A fork instruction for execution on a multithreaded microprocessor and occupying a single instruction issue slot is disclosed. The fork instruction, executing in a parent thread, includes a first operand specifying the initial instruction address of a new thread and...	03/27/2012
8145882	Apparatus and method for processing template based user defined instructions A system implemented in hardware includes a main processing core decoding instructions for out of order execution. The instructions include template based user defined instructions. A user execution block executes the template based user defined instructions. An int...	03/27/2012
8051320	Clock ratio controller for dynamic voltage and frequency scaled digital systems, and applications thereof The present invention provides a clock ratio controller for dynamic voltage and frequency scaled digital systems, and applications thereof. In an embodiment, a digital system is provided that includes a first digital circuit that operates at a first rate determined ...	11/01/2011
7990989	Transaction selector employing transaction queue group priorities in multi-port switch An apparatus for selecting one of a plurality of transaction queues from which to transmit a transaction out of a port of a switch. The apparatus includes a group indicator, for each of the queues, for indicating which one of a plurality of groups of the queues the ...	08/02/2011
7917699	Apparatus and method for controlling the exclusivity mode of a level-two cache A method of controlling the exclusivity mode of a level-two cache includes generating level-two cache exclusivity control information at a processor in response to an exclusivity mode indicator, and utilizing the level-two cache exclusivity control information to co...	03/29/2011
7770156	Dynamic selection of a compression algorithm for trace data A tracing system includes a trace bus and compression selection circuitry. The compression selection circuitry is configured to receive a trace data input from a source of trace data and determines a compression method for a piece of trace data selected for transmis...	08/03/2010
7752627	Leaky-bucket thread scheduler in a multithreading microprocessor A leaky-bucket style thread scheduler for scheduling concurrent execution of multiple threads in a microprocessor is provided. The execution pipeline notifies the scheduler when it has completed instructions. The scheduler maintains a virtual water level for each th...	07/06/2010
7747840	Method for latest producer tracking in an out-of-order processor, and applications thereof Methods for latest producer tracking in a processor. In one embodiment, the method includes the steps of (1) writing a physical register identification value in a first register rename map location specified by a first instruction, (2) writing a first in-register st...	06/29/2010
7739484	Instruction encoding to indicate whether to store argument registers as static registers and return address in subroutine stack A method and apparatus provide means for saving and restoring processor register values and allocating and deallocating stack memory. A first field of a save instruction encodes whether a value in a register of a processor is saved as a static value. A second field ...	06/15/2010
7721127	Multithreaded dynamic voltage-frequency scaling microprocessor A multithreaded microprocessor includes a thread scheduler and voltage-frequency scheduler (VFS). The thread scheduler uses application-specified QoS requirements, which include required instruction completion rates, and instruction completion information from execu...	05/18/2010
7721075	Conditional branch execution in a processor having a write-tie instruction and a data mover engine that associates register addresses with memory addresses A RISC processor having a data mover engine and instructions that associate register addresses with memory addresses. In an embodiment, the instructions include a read-tie instruction, a single write-tie instruction, a dual write-tie instruction, and an untie instru...	05/18/2010
7721074	Conditional branch execution in a processor having a read-tie instruction and a data mover engine that associates register addresses with memory addresses A RISC processor having a data mover engine and instructions that associate register addresses with memory addresses. In an embodiment, the instructions include a read-tie instruction, a single write-tie instruction, a dual write-tie instruction, and an untie instru...	05/18/2010
7721073	Conditional branch execution in a processor having a data mover engine that associates register addresses with memory addresses A RISC processor having a data moving engine and instructions that associate register addresses with memory addresses. In an embodiment, the instructions include a read-tie instruction, a single write-tie instruction, a dual write-tie instruction, and an untie instr...	05/18/2010
7721071	System and method for propagating operand availability prediction bits with instructions through a pipeline in an out-of-order processor A processor core and a method for distributive scoreboard scheduling in an out-of-order processor pipeline are described herein. In an embodiment, control logic appends operand availability bits to each instruction. The appended operand availability bits form a dist...	05/18/2010
7711934	Processor core and method for managing branch misprediction in an out-of-order processor pipeline A processor core and method for managing branch misprediction in an out-of-order processor pipeline. In one embodiment, the pipeline of the processor core includes a front-end instruction fetch portion, a back-end instruction execution portion, and pipeline control ...	05/04/2010
7702055	Apparatus and method for tracing processor state from multiple clock domains A method of tracing processor data includes receiving a first trace stream from a first processor operating in response to a first clock and a second trace stream from a second processor operating in response to a second clock. The first trace stream is routed to a ...	04/20/2010
7647475	System for synchronizing an in-order co-processor with an out-of-order processor using a co-processor interface store data queue A processor includes a coprocessor interface unit that couples a coprocessor that executes instructions in-program order to an execution unit that executes instructions out-of-program order. The coprocessor interface unit includes a coprocessor store data queue. If ...	01/12/2010
7644237	Method and apparatus for global ordering to insure latency independent coherence A method and apparatus is described for insuring coherency between memories in a multi-agent system where the agents are interconnected by one or more fabrics. A global arbiter is used to segment coherency into three phases: request; snoop; and response, and to appl...	01/05/2010
7613966	Hyperjtag system including debug probe, on-chip instrumentation, and protocol A system for simultaneously interfacing multiple test instruments with multiple processor cores includes an on-chip instrumentation, a probe, and a connection mechanism for providing a transmission path between the probe and the on-chip instrumentation. The on-chip ...	11/03/2009
7600135	Apparatus and method for software specified power management performance using low power virtual threads A processor comprises a software control module specifying a power performance metric. A policy manager is responsive to the software control module. A dispatch scheduler is responsive to the policy manager to operate the processor in accordance with the power perfo...	10/06/2009
7552261	Configurable prioritization of core generated interrupts A method and apparatus for generating an interrupt vector associated with either core (internal) generated or off-core (external) generated interrupts is provided. The apparatus includes a number of programmable interrupt priority level fields for storing priority l...	06/23/2009
7551626	Queueing system for processors in packet routing operations In a data-packet processor, a configurable queueing system for packet accounting during processing has a plurality of queues arranged in one or more clusters, an identification mechanism for creating a packet identifier for arriving packets, insertion logic for inse...	06/23/2009
7546443	Providing extended precision in SIMD vector arithmetic operations The present invention provides extended precision in SIMD arithmetic operations in a processor having a register file and an accumulator. A first set of data elements and a second set of data elements are loaded into first and second vector registers, respectively. ...	06/09/2009
7543207	Full scan solution for latched-based design A full-scan latch is provided that may be used to incorporate design for test functionality in an integrated circuit. The full-scan latch includes a shadow latch, a multiplexer, and a slave latch. The full-scan latch has a test mode and a normal mode. When in the no...	06/02/2009
7533220	Microprocessor with improved data stream prefetching A microprocessor coupled to a system memory has a memory subsystem with a translation look-aside buffer (TLB) for storing TLB information. The microprocessor also includes an instruction decode unit that decodes an instruction that specifies a data stream in the sys...	05/12/2009
7533219	Microprocessor having a power-saving instruction cache way predictor and instruction replacement scheme Microprocessor having a power-saving instruction cache way predictor and instruction replacement scheme. In one embodiment, the processor includes a multi-way set associative cache, a way predictor, a policy counter, and a cache refill circuit. The policy counter pr...	05/12/2009
7529915	Context switching processor with multiple context control register sets including write address register identifying destination register for waiting context to store returned data from external source Systems and methods for managing context switches among threads in a processing system. A processor may perform a context switch between threads using separate context registers. A context switch allows a processor to switch from processing a thread that is waiting ...	05/05/2009
7529907	Method and apparatus for improved computer load and store operations Load and store operations in computer systems are extended to provide for Stream Load and Store and Masked Load and Store. In Stream operations a CPU executes a Stream instruction that indicates by appropriate arguments a first address in memory or a first register ...	05/05/2009
7512740	Microprocessor with improved data stream prefetching A microprocessor coupled to a system memory by a bus includes an instruction decode unit that decodes an instruction that specifies a data stream in the system memory and a stream prefetch priority. The microprocessor also includes a load/store unit that generates l...	03/31/2009
7509459	Microprocessor with improved data stream prefetching A microprocessor has a plurality of stream prefetch engines for prefetching a respective data stream from the system memory into the microprocessor cache memory and an instruction decoder that decodes instructions of the microprocessor instruction set. The instructi...	03/24/2009
7509456	Apparatus and method for discovering a scratch pad memory configuration The invention includes a method of debugging an embedded processor. Scratch pad memory of an embedded processor is accessed to form a configuration file characterizing the configuration of scratch pad regions of the scratch pad memory. The embedded processor is debu...	03/24/2009
7509447	Barrel-incrementer-based round-robin apparatus and instruction dispatch scheduler employing same for use in multithreading microprocessor An apparatus for selecting one of N requestors of a shared resource in a round-robin fashion is disclosed. One or more of the N requestors may be disabled from being selected in a selection cycle. The apparatus includes a first input that receives a first value spec...	03/24/2009
7506140	Return data selector employing barrel-incrementer-based round-robin apparatus A return data selector is disclosed. A pipelined microprocessor includes N functional units that request to return data to the pipeline. In a given selection cycle, some of the functional units may not be requesting to return data. The return data selector includes ...	03/17/2009
7506106	Microprocessor with improved data stream prefetching A microprocessor has a data stream prefetch unit for processing a data stream prefetch instruction. The instruction specifies a data stream and a speculative stream hit policy indicator. If a load instruction hits in the data stream, then if the load is non-speculat...	03/17/2009
7502876	Background memory manager that determines if data structures fits in memory with memory state transactions map A background memory manager (BMM) for managing a memory in a data processing system has circuitry for transferring data to and from an outside device and to and from a memory, a memory state map associated with the memory, and a communication link to a processor. Th...	03/10/2009
7496771	Processor accessing a scratch pad on-demand to reduce power consumption The present invention provides processing systems, apparatuses, and methods that access a scratch pad on-demand to reduce power consumption. In an embodiment, an instruction fetch unit initiates an instruction fetch. When a scratch pad is enabled, an instruction is ...	02/24/2009
7490230	Fetch director employing barrel-incrementer-based round-robin apparatus for use in multithreading microprocessor A fetch director in a multithreaded microprocessor that concurrently executes instructions of N threads is disclosed. The N threads request to fetch instructions from an instruction cache. In a given selection cycle, some of the threads may not be requesting to fetc...	02/10/2009
7487339	Method and apparatus for binding shadow registers to vectored interrupts A method and apparatus within a processing system is provided for associating shadow register sets with interrupt routines. The invention includes a vector generator that receives interrupts, and generates exception vectors to call interrupt routines that correspond...	02/03/2009
7487332	Method and apparatus for binding shadow registers to vectored interrupts A method and apparatus within a processing system is provided for associating shadow register sets with interrupt routines. The invention includes a vector generator that receives interrupts, and generates exception vectors to call interrupt routines that correspond...	02/03/2009
7480769	Microprocessor with improved data stream prefetching A microprocessor coupled to a system memory includes a load request signal that requests data be loaded from the system memory into the microprocessor in response to a load instruction. The load request signal includes a load virtual page address. The microprocessor...	01/20/2009

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Assignee: Mips Technologies, Inc.