Assignee: Micron Technology Inc.

Location: Boise, ID
No. of patents: 2877

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Number	Title	Issue Date
7990772	Memory device having improved programming operation Some embodiments include methods and devices having a module and memory cells. The module is configured to reduce the amount of electrons in the sources and drains of the memory cells during a programming operation. ...	08/02/2011
7978721	Multi-serial interface stacked-die memory architecture Systems and methods disclosed herein substantially concurrently transfer a plurality of streams of commands, addresses, and/or data across a corresponding plurality of serialized communication link interfaces (SCLIs) between one or more originating devices or destin...	07/12/2011
7892942	Methods of forming semiconductor constructions, and methods of forming isolation regions Some embodiments include methods of forming isolation regions in which spin-on material (for example, polysilazane) is converted to a silicon dioxide-containing composition. The conversion may utilize one or more oxygen-containing species (such as ozone) and a tempe...	02/22/2011
7770079	Error scanning in flash memory Various embodiments include methods, apparatus, and systems to scan at least a portion of a memory device for potential errors when a condition for scanning is met. The condition may be dependent on one or more of a number of read operations, a number of write opera...	08/03/2010
7767544	Semiconductor fabrication method and system Embodiments of the present invention are generally directed to a method for manufacturing a semiconductor device. In one embodiment, the method includes providing a substrate that includes a via or interconnect. In this embodiment, the method also includes forming a...	08/03/2010
7688378	Imager method and apparatus employing photonic crystals An image sensor and a method of forming an image sensor. The image sensor includes an array of pixel cells at a surface of a substrate. Each pixel cell has a photo-conversion device. At least one a micro-electro-mechanical system (MEMS) element including a photonic ...	03/30/2010
7683306	Dual conversion gain gate and capacitor combination A pixel cell array architecture having a dual conversion gain. A dual conversion gain element is coupled between a floating diffusion region and a respective storage capacitor. The dual conversion gain element having a control gate switches in the capacitance of the...	03/23/2010
7671914	Increasing readout speed in CMOS APS sensors through block readout A method and associated architecture for dividing column readout circuitry in an active pixel sensor in a manner which reduces the parasitic capacitance on the readout line. In a preferred implementation, column readout circuits are grouped in blocks and provided wi...	03/02/2010
7671644	Process insensitive delay line A delay line including a phase detector having two inputs and one output. The first input of the phase detector is connected to an input of the delay line. The second input of the phase detector is connected to an output of the delay line. The output of the phase de...	03/02/2010
7663925	Method and apparatus for programming flash memory A method and apparatus that provides the ability to control programming pulses having different widths and/or voltages in a flash memory device. The widths and/or voltage levels of programming pulses are set to achieve programming of all memory cells of an array usi...	02/16/2010
7655507	Microelectronic imaging units and methods of manufacturing microelectronic imaging units Methods for manufacturing microelectronic imaging units and microelectronic imaging units that are formed using such methods are disclosed herein. In one embodiment, a method includes coupling a plurality of singulated imaging dies to a support member. The individua...	02/02/2010
7619670	Rolling shutter for prevention of blooming A rolling shutter technique for a pixel array is described in which multiple rows of the array are hard reset as the shutter moves down the array. As the rolling shutter progresses down the array, each row is hard reset multiple times before its integration period b...	11/17/2009
7616474	Offset compensated sensing for magnetic random access memory An offset compensated memory element voltage supply including a differential amplifier with a compensation circuit, and a transistor with a gate connected to the output of the differential amplifier. The compensation circuit of the differential amplifier includes a ...	11/10/2009
7596052	Method and apparatus for reducing oscillation in synchronous circuits Control signal oscillation filtering circuits, delay-locked loops, clock synchronization methods and devices and system incorporating control signal oscillation filtering circuits is described. An oscillation filtering circuit includes a first oscillation filter con...	09/29/2009
7505357	Column/row redundancy architecture using latches programmed from a look up table A scheme for defective memory column or row substitution is disclosed which uses a programmable look-up table to store new addresses for column selection when certain column or row addresses are received. The new addresses are loaded into a programmable fuse latch e...	03/17/2009
7505317	Method, apparatus, and system for providing initial state random access memory A memory device comprising memory cells having volatile and non-volatile memory portions. The volatile memory portion of each cell includes circuitry for performing RAM functions while the non-volatile memory portion comprises circuitry defining pre-coded data. The ...	03/17/2009
7492196	Low injection charge pump A fast acting charge pump is provided which is suitable for use in a locked loop circuit where very short duration first and second adjustment pulses are produced by a phase detector. The first complement of the second adjustment pulses are used to switch the output...	02/17/2009
7489000	Capacitor structures with oxynitride layer between capacitor plate and capacitor dielectric layer Methods for fuming dielectric layers over polysilicon substrates, useful in the construction of capacitors and other semiconductor circuit components are provided. A self-limiting nitric oxide (NO) anneal of a polysilicon layer such as an HSG polysilicon capacitor e...	02/10/2009
7464308	CAM expected address search testmode A CAM device that performs operations on-chip during testing. The CAM device can, for example, include circuitry that compares search results with an expected address to determine whether the expected address is defective. The CAM can be tested by applying search da...	12/09/2008
7464231	Method for self-timed data ordering for multi-data rate memories A self-timed data ordering method and circuit for multi-data rate memories orders a plurality of data words substantially simultaneously retrieved during successive read operations of a memory device. A data word ordering designator is stored from each of the succes...	12/09/2008
7463542	Temperature sensing device in an integrated circuit A temperature sensing device can be embedded in a memory circuit in order to sense the temperature of the memory circuit. One oscillator generates a temperature variable signal that increases frequency as the temperature of the oscillator increases and decreases fre...	12/09/2008
7463520	Memory device with variable trim settings A memory device includes a memory array including a plurality of cells. The cells are divided into a plurality of subsets. Each subset has at least one associated trim parameter. The trim parameter for each subset is stored in the memory array within the associated ...	12/09/2008
7463367	Estimating overlay error and optical aberrations Aberration marks, which may be used in conjunction with lenses in optical photolithography systems, may assist in estimating overlay errors and optical aberrations. Aberration marks may include an inner polygon pattern and an outer polygon pattern, wherein each of t...	12/09/2008
7463099	Phase detector for reducing noise The present invention provides a method and an apparatus for reducing noise. The apparatus includes a phase detector adapted to determine a phase difference between a first and a second signal, a first circuit adapted to generate a control signal based upon the dete...	12/09/2008
7463052	Method and circuit for off chip driver control, and memory device using same An off chip driver impedance adjustment circuit includes a storage circuit adapted to receive and store a drive strength adjustment word. A counter circuit is coupled to the storage circuit to receive the drive strength adjustment word and develops a drive strength ...	12/09/2008
7462935	Structure and method for forming a capacitively coupled chip-to-chip signaling interface A system and method for providing capacitively-coupled signaling in a system-in-package (SiP) device is disclosed. In one embodiment, the system includes a first semiconductor device and an opposing second semiconductor device spaced apart from the first device, a d...	12/09/2008
7462559	Systems and methods for forming metal-containing layers using vapor deposition processes A method of forming (and an apparatus for forming) a metal containing layer on a substrate, particularly a semiconductor substrate or substrate assembly for use in manufacturing a semiconductor or memory device structure, using one or more homoleptic and/or heterole...	12/09/2008
7462534	Methods of forming memory circuitry The invention includes methods of forming memory circuitry. In one implementation, a substrate is provided which has a memory array circuitry area and a peripheral circuitry area. The memory array circuitry area comprises transistor gate lines having a first minimum...	12/09/2008
7462510	Standoffs for centralizing internals in packaging process A semiconductor device, semiconductor die package, mold tooling, and methods of fabricating the device and packages are provided. In one embodiment, the semiconductor device comprises a pair of semiconductor dies mounted on opposing sides of a flexible tape substrat...	12/09/2008
7462088	Method for making large-area FED apparatus A method is provided for forming and associating a lower section of a large-area field emission device (“FED”) that is sealed under a predetermined level of vacuum pressure with an upper section of a large-area FED. The upper section of the FED includes a facepl...	12/09/2008
7461320	Memory system and method having selective ECC during low power refresh A computer system includes a processor coupled to a DRAM through a memory controller. The processor switches the DRAM to a low power refresh mode in which DRAM cells are refreshed at a sufficiently low rate that data retention errors may occur. Prior to switching th...	12/02/2008
7461306	Output data compression scheme using tri-state A memory device uses data compression to read data from an array of the memory during testing. The compressed data is either a logic one, logic zero or tri-state, depending upon the data read from the array. Output drivers of the memory are placed in a tri-state con...	12/02/2008
7461286	System and method for using a learning sequence to establish communications on a high-speed nonsynchronous interface in the absence of clock forwarding A memory system includes a memory hub controller that sends write data to a plurality of memory modules through a downstream data bus and receives read data from the memory modules through an upstream data bus. The memory hub controller includes a receiver coupled t...	12/02/2008
7461188	Capacitive multidrop bus compensation The signal integrity of a high speed heavily loaded multidrop memory bus is often degraded due the numerous impedance mismatches. The impedance mismatches causes the bus to exhibit a nonlinear frequency response, which diminishes signal integrity and limits the band...	12/02/2008
7461139	Network computer providing mass storage, broadband access, and other enhanced functionality A network computer system includes a processor and a memory device coupled to the processor. The memory device contains an embedded operating system that is executed by the processor, the embedded operating system including at least one system parameter. A first res...	12/02/2008
7460432	Sequential access memory with system and method A sequential access memory (“SAM”) device, system and method is provided that includes a memory array configured to store a group of bytes on each of a plurality of rows. A plurality of bit-lines transfer each of the group of bytes into and out of the memory arr...	12/02/2008
7460430	Memory devices having reduced coupling noise between wordlines Memory devices configured to reduce coupling noise between adjacent wordlines in a memory array. More specifically, wordline drivers are interleaved such that adjacent wordlines are driven by wordline drivers enabled by different row decoders. Each wordline driver i...	12/02/2008
7460429	Circuit and method for reducing power in a memory device during standby modes A memory device responsive to standby mode commands for reducing internal operational power on a memory device is disclosed. The memory device includes a circuit for reducing power during a standby mode with the circuit including a reference with at least first and ...	12/02/2008
7460398	Programming a memory with varying bits per cell Memory devices adapted to receive and transmit analog data signals representative of two or more bits, such as to facilitate increases in data transfer rates relative to devices communicating data signals indicative of individual bits. A controller and a read/write ...	12/02/2008
7459944	Low current wide VREF range input buffer A low-current input buffer is disclosed. The buffer uses self-biased N and P channel differential pairs with their outputs tied together. The self-biasing assists in reducing current consumption. The combination of N and P-channel differential pairs results in symme...	12/02/2008

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Assignee: Micron Technology Inc.