Assignee: Micron Semiconductor, Inc.

Location: Boise, ID
No. of patents: 155

Browse patents
Browse applications

Number	Title	Issue Date
6312557	Method and apparatus for using photoemission to determine the endpoint of an etch process A method and apparatus for using photoemission to determine the endpoint of a dry etch process. In one embodiment, the endpoint of a dry etch process is determined when the dry etch process is acting on a substrate comprising a layer of a first material o...	11/06/2001
6244498	Ultrasonic vibration mode for wire bonding A method and apparatus for creating second order vibrational modes. The apparatus includes a signal generator, a piezoelectric transducer, a plurality of wave propagating beams and reflecting boards. An electric field applied by the signal generator to th...	06/12/2001
5763286	Process for manufacturing a DRAM capacitor having an annularly-grooved, cup-shaped storage-node plate which stores charge on inner and outer surfaces This invention is a process for fabricating a DRAM capacitor having an annularly-grooved, cup-shaped storage-node plate and a cell plate which covers both inner and outer surfaces of the storage-node plate. A plurality of oxide layers having alternately-v...	06/09/1998
5696014	Method for increasing capacitance of an HSG rugged capacitor using a phosphine rich oxidation and subsequent wet etch A capacitor and method for forming the capacitor having HSG polysilicon with reduced dielectric bridging, increased capacitance, and minimal depletion effects. A first polysilicon layer is deposited and doped with impurities to increase conductivity. A se...	12/09/1997
5636175	Row decoder/driver circuit for determining non selected wordlines and for driving non-selected wordlines to a potential less than the lowest potential of the digit lines A semiconductor integrated circuit having a decode circuit for selecting selected and non-selected wordlines and having a driver circuit for driving a potential to the non-selected wordlines which is less than the lowest potential to which any digit lines...	06/03/1997
5541137	Method of forming improved contacts from polysilicon to silicon or other polysilicon layers The method of the present invention introduces a method of forming conductively doped contacts on a supporting substrate in a semiconductor device that minimizes the lateral out-diffusion of the conductive dopants and also provides for a low resistive con...	07/30/1996
5504831	System for compensating against wafer edge heat loss in rapid thermal processing A method for compensating against wafer edge heat loss during rapid thermal processing includes a semiconductor wafer that is exposed to uniform radiant energy across the entire wafer surface. The wafer is exposed by projecting a radiant energy image onto...	04/02/1996
5496762	Highly resistive structures for integrated circuits and method of manufacturing the same This invention is a process for making resistor structures having high stability and reliability characteristics. Process parameters are easily modifiable to adjust the resistivity of the structures. A layer of titanium nitride, which may contain certain ...	03/05/1996
5496775	Semiconductor device having ball-bonded pads An integrated circuit (IC) device comprises towers of bonded gold balls located on each bond pad. The towers allow for early encapsulation of the IC die. The IC can then be tested and attached to tab tape or a printed circuit board without particulate con...	03/05/1996
5494841	Split-polysilicon CMOS process for multi-megabit dynamic memories incorporating stacked container capacitor cells This invention is a process for manufacturing dynamic random access memories using stacked container capacitor cells in a split-polysilicon CMOS manufacturing flow. The split-polysilicon flow denotes that N-channel and P-channel transistor gates are forme...	02/27/1996
5492853	Method of forming a contact using a trench and an insulation layer during the formation of a semiconductor device A structure and process for forming a contact to a semiconductor substrate on a semiconductor device comprises the step of forming a patterned mask over a semiconductor substrate and over a field oxide region, then etching the semiconductor substrate and ...	02/20/1996
5492597	Method of etching WSi_x films The present invention teaches a method for etching a tungsten silicide (WSix) film overlying a polysilicon film in an enclosed chamber during a semiconductor fabrication process, by the steps of: providing a patterned mask overlying the WSi	02/20/1996
5484314	Micro-pillar fabrication utilizing a stereolithographic printing process Another aspect of the present invention comprises a method for fabricating columnar supports used for an evacuated display, in which an electrode plate is covered with a layer of material having a depth. The material is used to form the columnar supports,...	01/16/1996
5469393	Circuit and method for decreasing the cell margin during a test mode The invention is a monolithic memory device having a circuit and a method for decreasing the cell margin during a test mode. Decreasing the cell margin stresses the memory device during the test mode greater than a stress experienced during normal operati...	11/21/1995
5466639	Double mask process for forming trenches and contacts during the formation of a semiconductor memory device A method of forming contact to a semiconductor memory device feature comprises the steps of forming a first oxide layer over a feature such as a semiconductor substrate or a conductive line or plate, then forming a hard mask over the first oxide layer. A ...	11/14/1995
5465232	Sense circuit for tracking charge transfer through access transistors in a dynamic random access memory A simple, low-power sense circuit is disclosed that accurately tracks charge transfer between the capacitor of a dynamic random access memory cell and its associated digit line. The circuit, which is preferably located in the peripheral circuitry, employs...	11/07/1995
5464031	Method of chamber cleaning in MOCVD applications The invention is a process for cleaning a chamber after a chemical vapor deposition has been performed therein. A residue formed during the deposition is combined with a reactive species to form a gas containing an organic substance once found in the resi...	11/07/1995
5455801	Circuit having a control array of memory cells and a current source and a method for generating a self-refresh timing signal A method and circuit for generating a self-refresh mode signal and a self-refresh cycle signal. The circuit is a dynamic random access memory (DRAM) device having a control array of control cells charged to a potential by a current source and having a mon...	10/03/1995
5450355	Multi-port memory device A multi-port memory device includes a row-column array, a random access port, a plurality of bidirectional serial access memory (SAM) ports, and a switching network. There is one SAM port for each of a plurality of sets of columns. The switching network s...	09/12/1995
5449433	Use of a high density plasma source having an electrostatic shield for anisotropic polysilicon etching over topography A method for etching structures having topography, which structures are comprised of polysilicon disposed over an oxide, by placing an electrostatic shield on a high density source etcher while etching the structures. The etch involves the removal of the ...	09/12/1995
5446367	Reducing current supplied to an integrated circuit An integrated circuit of the present invention includes power regulating circuitry for reducing preregulator bias current. In one embodiment, power regulating circuitry includes a two stage preregulator for supplying current to a charge pump and a primary...	08/29/1995
5446671	Look-ahead method for maintaining optimum queued quantities of in-process parts at a manufacturing bottleneck This invention is a look-ahead method for determining optimum production schedules for each production step based on factory-wide monitoring of in-process part queues at all potential production bottlenecks. For each product having associated therewith a ...	08/29/1995
5444279	Floating gate memory device having discontinuous gate oxide thickness over the channel region A method and structure for a programmable read-only memory comprises a thin gate oxide over a source region and a thick gate oxide over the drain region. A semiconductor substrate is lightly doped and has regions of thin sacrificial oxide overlying what w...	08/22/1995
5442642	Test signal generator on substrate to test A test system is added to a substrate and a test mode of operation is added to the timing and control functions of a system on the substrate. When a multifunctional system on the substrate is tested, a first functional subsystem is connected to an externa...	08/15/1995
5440519	Switched memory expansion buffer A module such as a SIMM or other type of memory module is provided with supply power at a higher potential than the operating potential of semiconductor memory devices on the module. A voltage regulator circuit on the module reduces the potential supplied...	08/08/1995
5439835	Process for DRAM incorporating a high-energy, oblique P-type implant for both field isolation and punchthrough This invention is a process for fabricating a CMOS dynamic random access memory (DRAM) wherein a high-energy, oblique P-type implant is employed for punchthrough protection and field isolation enhancement or alternatively for punchthrough protection and a...	08/08/1995
5438016	Method of semiconductor device isolation employing polysilicon layer for field oxide formation A process for forming field oxide on a semiconductor substrate having reduced field oxide thinning comprises forming an oxide layer over a semiconductor substrate, and forming a protective layer over the oxide layer. A mask is formed over the protective l...	08/01/1995
5438019	Large area thin film growing method High quality silicon thin films are formed on a substrate in a conventional chemical vapor deposition reactor using silicon hydride source gas, and allowing adsorption of the deposition at low temperature before decomposition at a higher temperature. The ...	08/01/1995
5428310	Voltage compensating delay element A signal-delaying capacitive circuit applied to a node in a microcircuit device is immunized against the variation of the supply voltage by a metal-oxide semiconductor connected in series between the node and the signal-delaying capacitive circuit. The ga...	06/27/1995
5425392	Method DRAM polycide rowline formation The present invention teaches a method for reducing sheet resistance in the fabrication of semiconductor wafers. A silicon substrate having a gate oxide layer thereon is provided in a chamber. Subsequently, a polysilicon layer is formed superjacent the ga...	06/20/1995
5424672	Low current redundancy fuse assembly In a microcircuit device such as a memory chip, where a bank of fuse-controlled latch pulse routing-circuits are used to program redundant circuits or other programming options with every memory cycle or multiple thereof, the amount of current drawn by ev...	06/13/1995
5422499	Sixteen megabit static random access memory (SRAM) cell A new and improved static random access memory (SRAM) cell wherein separate regions of polysilicon are formed over a silicon substrate and are separated by defined openings therein into which oxide filler material is introduced to render the regions of po...	06/06/1995
5420061	Method for improving latchup immunity in a dual-polysilicon gate process The invention is a method for creating a portion of an integrated circuit on a semiconductor wafer. The invention comprises doping a substrate to form a doped well region having an opposite conductivity type than the substrate. Separate photomasking steps...	05/30/1995
5418180	Process for fabricating storage capacitor structures using CVD tin on hemispherical grain silicon An embodiment of the present invention depicts a storage capacitor comprising: a bottom plate structure having a hemispherical grain silicon surface; a titanium nitride layer adjacent and coextensive the hemispherical grain silicon; an insulating layer ad...	05/23/1995
5416363	Logic circuit initialization A circuit, responsive to the application of primary power, generates signals to establish the initial state of a logic circuit. Generated signals are interposed on the logic circuit's input signal line until initialization is complete. After initializatio...	05/16/1995
5416048	Method to slope conductor profile prior to dielectric deposition to improve dielectric step-coverage A process for semiconductor manufacture in which the top corners of conductive features are preferentially etched compared to the etch rate of the vertical and horizontal surfaces, thereby creating a sloped (prograde) profile, i.e., facets. The material r...	05/16/1995
5416348	Current leakage reduction at the storage node diffusion region of a stacked-trench DRAM cell by selectively oxidizing the floor of the trench This invention constitutes a process for fabricating a structure which, when incorporated in an integrated circuit, will reduce current leakage into the substrate from transistor source/drain regions. The structure is particularly useful in dynamic random...	05/16/1995
5414376	Programmable logic device macrocell having exclusive lines for feedback and external input, and a node which is selectively shared for registered output and external input An improved programmable logic device (PLD) having a macrocell operable in a registered mode is disclosed. The improved PLD has exclusive lines for both registered feedback and for external input, both of which are fed into a single multiplexer. The outpu...	05/09/1995
5410508	Pumped wordlines The invention is a circuit and method for maintaining a negative potential, with respect to the digit line potential, on non-selected wordlines....	04/25/1995
5409858	Method for optimizing thermal budgets in fabricating semiconductors A method for fabricating semiconductors is provided in which a conformal layer is formed superjacent at least two conductive layers. The conformal layer has a thickness of at least 50 Å. A barrier layer is then formed superjacent the conformal layer to p...	04/25/1995

«First «Previous1 2 3 4 Next»Last»

PatentStorm

Quotables

PatentStorm News

Assignee: Micron Semiconductor, Inc.