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| Number | Title | Issue Date |
| 7609567 | System and method for simulating an aspect of a memory circuit A system and method are provided for simulating an aspect of a memory circuit. Included is an interface circuit that is in communication with a plurality of memory circuits and a system. Such interface circuit is operable to interface the memory circuits and the sys... | 10/27/2009 |
| 7599205 | Methods and apparatus of stacking DRAMs Large capacity memory systems are constructed using stacked memory integrated circuits or chips. The stacked memory chips are constructed in such a way that eliminates problems such as signal integrity while still meeting current and future memory standards. ... | 10/06/2009 |
| 7590796 | System and method for power management in memory systems A memory circuit power management system and method are provided. In use, an interface circuit is in communication with a plurality of physical memory circuits and a system. The interface circuit is operable to interface the physical memory circuits and the system f... | 09/15/2009 |
| 7581127 | Interface circuit system and method for performing power saving operations during a command-related latency A memory circuit power management system and method are provided. In use, an interface circuit is in communication with a plurality of memory circuits and a system. The interface circuit is operable to interface the memory circuits and the system for performing a po... | 08/25/2009 |
| 7580312 | Power saving system and method for use with a plurality of memory circuits A power saving system and method are provided. In use, at least one of a plurality of memory circuits is identified that is not currently being accessed. In response to the identification of the at least one memory circuit, a power saving operation is initiated in a... | 08/25/2009 |
| 7515453 | Integrated memory core and memory interface circuit A memory device comprises a first and second integrated circuit dies. The first integrated circuit die comprises a memory core as well as a first interface circuit. The first interface circuit permits full access to the memory cells (e.g., reading, writing, activati... | 04/07/2009 |
| 7472220 | Interface circuit system and method for performing power management operations utilizing power management signals A memory circuit power management system and method are provided. In use, an interface circuit is in communication with a plurality of memory circuits and a system. The interface circuit is operable to interface the memory circuits and the system for communicating a... | 12/30/2008 |
| 7392338 | Interface circuit system and method for autonomously performing power management operations in conjunction with a plurality of memory circuits A memory circuit power management system and method are provided. In use, an interface circuit is in communication with a plurality of memory circuits and a system. The interface circuit is operable to interface the memory circuits and the system for autonomously pe... | 06/24/2008 |
| 7386656 | Interface circuit system and method for performing power management operations in conjunction with only a portion of a memory circuit A memory circuit power management system and method are provided. An interface circuit is in communication with a plurality of memory circuits and a system. In use, the interface circuit is operable to perform a power management operation in association with only a ... | 06/10/2008 |
| 7379316 | Methods and apparatus of stacking DRAMs Large capacity memory systems are constructed using stacked memory integrated circuits or chips. The stacked memory chips are constructed in such a way that eliminates problems such as signal integrity while still meeting current and future memory standards. ... | 05/27/2008 |
