Assignee: Mentor Graphics Corporation

Location: Wilsonville, OR
No. of patents: 172

Number	Title	Issue Date
8185847	Pre-bias optical proximity correction A pre-bias optical proximity correction (OPC) method allows faster convergence during OPC iterations, providing an initial set of conditions to edge fragments of a layout based on density conditions near the edge fragments. ...	05/22/2012
8185368	Mixed-domain analog/RF simulation A simulation environment is disclosed wherein both analog and RF signals are simulated in a single flow by a mixed-domain simulator. The simulator includes a simulator kernel with an analog solver and an RF solver to allow both analog- and RF-type of signals to be s...	05/22/2012
8181129	Acyclic modeling of combinational loops Aspects of the present invention are directed to converting non-oscillatory combinational loops into acyclic circuits. Combinational loops may be modeled as state-holding elements where non-oscillatory loops are broken using edge-sensitive latches. In addition to pr...	05/15/2012
8171357	Generating test sets for diagnosing scan chain failures Embodiments of the disclosed technology comprise software-based techniques that can be used to improve scan chain test pattern generation and scan chain failure diagnosis resolution. For example, certain embodiments can be used to generate high quality chain diagnos...	05/01/2012
8166360	Direct logic diagnostics with signature-based fault dictionaries Disclosed herein are representative embodiments of methods, apparatus, and systems for performing diagnostic from signatures created during circuit testing. For example, in one exemplary method disclosed herein, a signature produced by a signature generator is recei...	04/24/2012
8166359	Selective per-cycle masking of scan chains for system level test Built-in self-test techniques for integrated circuits that address the issue of unknown states. Some implementations use a specialized scan chain selector coupled to a time compactor. The presence of the specialized scan chain selector increases the efficiency in ma...	04/24/2012
8165865	Modeling and simulation method A method for modeling and simulating a system comprising first and second interrelated components is disclosed. The method comprises modeling the behavior of said first and second components using first and second specifications. Each of said first and second specif...	04/24/2012
8161438	Determining mutual inductance between intentional inductors Various methods for analyzing mutual inductance in an integrated circuit layout are disclosed. In one exemplary embodiment, for example, circuit design information indicative of a first inductor and a second inductor is received. A dipole moment associated with the ...	04/17/2012
8161338	Modular compaction of test responses Exemplary embodiments of a compactor for compacting test responses are disclosed. In certain embodiments, the compactor comprises circular registers and has multiple inputs. The circular registers can have lengths that are relatively prime or prime. In certain imple...	04/17/2012
8151223	Source mask optimization for microcircuit design A method and apparatus for generating a source illuminator profile and a mask design, subsequently optimizing the source illuminator profile and mask design based upon a set of target intensity profiles. In various implementations, the Lagrange method of optimizatio...	04/03/2012
8146030	Interactive loop configuration in a behavioral synthesis tool A behavioral synthesis tool for generating an integrated circuit design is described. The behavioral synthesis tool allows a designer to interactively allocate loop configuration information without having to modify a source code description of the integrated circui...	03/27/2012
8122398	Conversion of circuit description to an abstract model of the circuit A system and method is disclosed for converting an existing circuit description from a lower level description, such as RTL, to a higher-level description, such as TLM, while raising the abstraction level. By changing the abstraction level, the conversion is not sim...	02/21/2012
8112686	Deterministic logic built-in self-test stimuli generation Techniques for storing and using compressed restrict values for selected scan chains and flip-flops, such that the states that need to be applied to those flip flops need not be solved by a linear equation system solver, such as a linear equation system solver provi...	02/07/2012
8108806	Contrast-based resolution enhancement for photolithographic processing A contrast-based resolution enhancing technology (RET) determines a distribution of contrast values for edge fragments in a design layout or portion thereof. Resolution enhancement is applied to the edge fragments in a way that increases the number of edge fragments...	01/31/2012
8108743	Method and apparatus for selectively compacting test responses A method and apparatus to compact test responses containing unknown values or multiple fault effects in a deterministic test environment. The proposed selective compactor employs a linear compactor with selection circuitry for selectively passing test responses to t...	01/31/2012
8108729	Memory-based trigger generation scheme in an emulation environment A system and method are disclosed for generating triggers within a hardware emulator. The system allows for dynamic reconfiguration of the trigger generation scheme during emulation. In one aspect, input probe signals are received on an address port to a memory from...	01/31/2012
8108198	Memory tracing in an emulation environment A system and method are disclosed to trace memory in a hardware emulator. In one aspect, a first Random Access Memory is used to store data associated with a user design during emulation. At any desired point in time, the contents of the first Random Access Memory a...	01/31/2012
8103988	Use of breakouts in printed circuit board designs An escape outline is provided to automatically identify escape traces of a breakout. Further, the escape outline can be used to associate desired properties with the identified escape traces and allows special behavior of the automatic and interactive routing routin...	01/24/2012
8103925	On-chip logic to support compressed X-masking for BIST Techniques are provided for X-masking using at least some masking information provided by on-chip logic, in lieu of masking information provided from off of the integrated circuit being tested. The masking information is provided by a masking information source on t...	01/24/2012
8099698	Verification test failure analysis Methods and apparatuses are provided that allow for efficient analysis of a graph describing tests, elements of a device design and test results. In various implementations of the invention, a relationship between the elements of a device design, and test results is...	01/17/2012
8099685	Model based microdevice design layout correction Shapes neighboring a potential manufacturing fault within a microdevice design layout are identified. Models are employed to determine the affect of the shapes upon the potential manufacturing fault. Possible adjustments to the shapes are modeled. The possible adjus...	01/17/2012
8099273	Compression of emulation trace data A system and method for compressing trace data from an emulation system. Scan chains may receive trace data from configurable logic blocks inside one or more emulation chips, and the data received from the scan chains may be compressed. Where delta compression is us...	01/17/2012
8091054	Synthesis strategies based on the appropriate use of inductance effects A method of optimizing the signal propagation speed on a wiring layout is provided. In general, the method accounts for and uses inductance effects caused by the propagation of a high-speed signal on a signal wire surrounded by parallel ground wires. In particular, ...	01/03/2012
8090935	Direct register access for host simulation Methods and apparatuses are provided that enable software designed to be operated with an embedded system to be tested in the absence of a physical embodiment of the embedded system. A simulation of the embedded system may be employed to operate the software. Variou...	01/03/2012
8086923	Accurately identifying failing scan bits in compression environments X-masking registers are added in front of a compactor in test data compression environment to remove unknown values. The X-masking registers block out some chains due to unknown values and select other chains to feed the compactor. This X-masking capability is used ...	12/27/2011
8086921	System and method of clocking an IP core during a debugging operation According to the invention, an IP core is clocked during a debugging operation by switching from the clock used for testing the device under test to a clock oscillator or any other free-running clock source. ...	12/27/2011
8084169	Dual metric OPC A technique for creating mask layout data to print a desired pattern of features via a photolithographic process includes defining one or more subresolution assist features (SRAFs) and performing OPC on printing features and the added SRAF features. ...	12/27/2011
8082141	Modelling and simulation method A method for simulating behavior of first and second interrelated components within a system. The method comprises modelling behavior of said first and second components using first and second functional specifications; simulating behavior of said first and second c...	12/20/2011
8073672	Managing communication bandwidth in co-verification of circuit designs Related communication signals between a simulator and an emulator are organized into logical channels. The signals in each channel are then be transmitted only as needed, reducing the use of the communication pathways between the simulator and the emulator. Further,...	12/06/2011
8065126	GUI-facilitated change management for vehicle electrical/electronic architecture design Disclosed herein are computer aided design (CAD) techniques to implement a unified data schema and graphical user interface (GUI) to link ECU/devices, in-vehicle communications, and vehicle harness information together with respect to architectural relation, perform...	11/22/2011
8060849	Automatic bus routing Particular embodiments generally relate to automatic routing of a bus in an integrated circuit design. In one embodiment, a method includes receiving a description of a circuit design. Buses are automatically detected based on pin adjacency in terms of distance betw...	11/15/2011
8060847	Clock model for formal verification of a digital circuit description An edge clock model is used to capture states from a logic-level simulation of a circuit description. The states are captured at clock edges, or transitions, according to an edge clock model based on a clock specification for the circuit description. The captured st...	11/15/2011
8060347	Complexity management for vehicle electrical/electronic architecture design Disclosed herein are computer aided design (CAD) techniques to implement a unified data schema and graphical user interface (GUI) to link ECU/devices, in-vehicle communications, and vehicle harness information together with respect to architectural relation, perform...	11/15/2011
8056022	Analysis optimizer A method of preparing a set of target layout data for the application of a photolithographic friendly design (LFD) analysis or other photolithographic analysis. The target layout data is revised to remove areas or features prior to performing the LFD analysis. The f...	11/08/2011
8051393	Gate modeling for semiconductor fabrication process effects In one embodiment, a method for determining a contour simplification of an object for a simulation is provided. An object in a layout of a transistor design to be created with the photolithographic process is determined. The object includes a width and a length in t...	11/01/2011
8051352	Timing-aware test generation and fault simulation Disclosed herein are exemplary methods, apparatus, and systems for performing timing-aware automatic test pattern generation (ATPG) that can be used, for example, to improve the quality of a test set generated for detecting delay defects or holding time defects. In ...	11/01/2011
8046653	Low power decompression of test cubes Disclosed below are representative embodiments of methods, apparatus, and systems used to generate test patterns for testing integrated circuits. Embodiments of the disclosed technology can be used to provide a low power test scheme and can be integrated with a vari...	10/25/2011
8046209	Coherent state among multiple simulation models in an EDA simulation environment A circuit design is simulated in a simulation environment. When a simulation model in the simulation environment transfers state information to a second simulation model, the simulation environment receives the state information and makes it available to the second ...	10/25/2011
8037429	Model-based SRAF insertion A system for producing mask layout data retrieves target layout data defining a pattern of features, or portion thereof and an optimized mask layout pattern that includes a number of printing and non-printing features. Mask layout data for one or more subresolution ...	10/11/2011
8024692	Modeling the skin effect using efficient conduction mode techniques Described herein are embodiments of methods for extracting various high frequency parameters for a circuit design. In one exemplary embodiment, circuit design information indicating at least a geometric layout of conductors in the circuit design and a desired freque...	09/20/2011

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Assignee: Mentor Graphics Corporation