Famous Patents
Pong, the Atari creation that launched the computer game craze, came with these instructions: "Avoid missing ball for high score."
PatentStorm News
Make the Most of Our Site
See this month's Top Inventors and Most Cited Patents.
Stay on top of the latest innovations by subscribing to an RSS feed.
Registered users: Manage your profile.
| Number | Title | Issue Date |
| 7629923 | Method and device for storing economically auxiliary correction data applied in global navigation satellite system A method applied in a Global Navigation Satellite System (GNSS) for minimizing storage of correction data is disclosed. The method comprises: determining the receiver position and satellite positions; determining a intermediate point according to the receiver positi... | 12/08/2009 |
| 7567054 | Control circuit and method of controlling rotation frequency of spindle in optical disc drive for reducing frequency difference of output signals respectively corresponding to different disc rotation modes A control circuit and a control method of controlling a rotation frequency of a spindle in an optical disc drive, the control circuit comprising: a spindle controller, electrically coupled to the spindle, for driving the spindle to rotate an optical disc according t... | 07/28/2009 |
| 7467020 | Method for gradually adjusting the volume level of a digital signal within a predefined time using a volume control circuit According to the claimed invention, a DSP is disclosed. The DSP comprises a processing unit for processing the data stream, a first memory coupled to the processing unit for storing a destination volume value, and a second memory coupled to the processing unit for s... | 12/16/2008 |
| 7457214 | Method for accessing a variable memory of an optical disk drive A method for accessing a variable memory of an optical disk drive includes utilizing the optical disk drive to read and write data of an optical disk, and identifying the type of the data. If the data is CD data, arrange writing variables from a first initial addres... | 11/25/2008 |
| 7457898 | Substitute SATA host for communicating with a SATA device A substitute serial advanced technology attachment (SATA) host is provided to communicate with a SATA device for facilitating communication with the SATA device even when a status flag of the SATA device indicates that the SATA device is busy. The SATA host is there... | 11/25/2008 |
| 7447846 | Non-volatile memory sharing apparatus for multiple processors and method thereof A multiple processor system includes a plurality of processors including a first processor and a second processor; a program code storage module coupled to the first processor, the program code storage module for storing program code including first program code for... | 11/04/2008 |
| 7434117 | Method and apparatus of determining bad frame indication for speech service in a wireless communication system A method of operating a receiver to determine a bad frame indication (BFI) of a received speech block includes decoding speech information bits of the received speech block; re-encoding the decoded speech information bits; comparing the received speech information b... | 10/07/2008 |
| 7421641 | Intelligent error checking method and mechanism An intelligent streaming media error check detection method and apparatus. The claimed embodiment discloses an apparatus and method where all streaming media are initially assumed to have compatible error checksums. A parameter W is initialized to zero. The paramete... | 09/02/2008 |
| 7413932 | Power amplifier having high heat dissipation A power amplifier includes a substrate, a heat sink for dissipating heat, and a heterojunction bipolar transistor (HBT) disposed on the substrate. The HBT includes a collector, a base, and at least an emitter. The power amplifier further includes an emitter electrod... | 08/19/2008 |
| 7412617 | Phase frequency detector with limited output pulse width and method thereof Phase frequency detectors with limited output pulse width and related methods are disclosed. The proposed phase frequency detector generates a first output signal and a second output signal corresponding to phase difference or frequency difference between a first si... | 08/12/2008 |
| 7397973 | Method for controlling interpolation direction and related device The present invention provides a method for controlling an interpolation direction of a pixel needing to be interpolated between a first row and a second row within an image. The image has a plurality of pixels arranged in a matrix format. The method includes calcul... | 07/08/2008 |
| 7397227 | Fast-disabled voltage regulator circuit with low-noise feedback loop and operating method thereof A low-noise voltage regulator circuit with quick disablement includes an amplifier for outputting a driving voltage according to a reference voltage, a feedback voltage on a feedback node, and an enable signal; an output transistor coupled among the amplifier, an ou... | 07/08/2008 |
| 7394715 | Memory system comprising memories with different capacities and storing and reading method thereof A memory system includes a first memory, a second memory, a determining unit, and an accessing unit. The capacity of the second memory is different from the capacity of the first memory. The first and the second memories are virtually partitioned into a first sectio... | 07/01/2008 |
| 7395462 | Defect estimation apparatus and related method A weighted defect estimating apparatus and a related method for determining a defect estimation value are disclosed. The weighted defect detecting apparatus includes: a defect detecting unit for generating a defect value when a defect in a predetermined region of an... | 07/01/2008 |
| 7391469 | Method and apparatus for video decoding and de-interlacing An apparatus for video decoding and de-interlacing contains a video decoder for decoding video data to generate decoded video data of a next picture; a storage device coupled to the video decoder, the storage device having four frame buffers for buffering the decode... | 06/24/2008 |
| 7376063 | Control circuit of optical storage device and method thereof A control circuit of an optical storage device includes a loop phase calculation unit for calculating a closed loop phase of a servo system according to at least one error signal of the servo system and a system control unit coupled to the loop phase calculation uni... | 05/20/2008 |
| 7375541 | Testing method utilizing at least one signal between integrated circuits, and integrated circuit and testing system thereof A testing method utilizing at least one signal between ICs includes: coupling at least one testing device to a plurality of ICs that are capable of being tested by the testing device, the ICs including at least a first IC and a second IC; coupling the second IC to t... | 05/20/2008 |
| 7362107 | Systems and methods for automatically eliminating imbalance between signals A calibrating system for automatically eliminating or reducing imbalance between a first signal and a second signal is disclosed. The calibrating system includes: a programmable delay module, receiving to the first and the second signals; a phase detecting module, c... | 04/22/2008 |
| 7348900 | Method and apparatus for encoding/decoding in fixed length A modulation method for a first data string having a plurality of symbols is disclosed. The method includes: appending a data string to the first data string to form a second data string; and converting the second data string to a code word sequence by converting ea... | 03/25/2008 |
| 7345964 | Method and related apparatus for deriving a tracking error signal A method for deriving a tracking error signal based on a first analog detection signal and a second analog detection signal. The method includes summing the first analog detection signal and the second analog detection signal to generate an analog sum signal. An ana... | 03/18/2008 |
| 7345963 | Method and related apparatus for deriving a tracking error signal A method for deriving a tracking error signal based on a first analog detection signal and a second analog detection signal. The method includes summing the first analog detection signal and the second analog detection signal to generate an analog sum signal. An ana... | 03/18/2008 |
| 7346727 | Method and system for control of a first device by data storage device through storing different values within task file register by the data storage device and reading task file register and performing corresponding predetermined operations by the first device via an IDE bus A system includes a first device; an Integrated Drive Electronics (IDE) bus; and a data storage device having a first task file register, the data storage device being coupled to the first device via the IDE bus for storing data within the data storage device as rec... | 03/18/2008 |
| 7333568 | Data slicer capable of calibrating current mismatch A data slicer includes a comparator coupled with an input signal and a reference signal for generating a sliced signal, a waveform generator for generating a calibration signal, a pulse extension device coupled to the comparator and the waveform generator for modify... | 02/19/2008 |
| 7333413 | Optical storage device rotation speed control apparatus and method A method for controlling the rotation speed of an optical storage device. In the first mode, a first signal is produced, and in the second mode, a second signal is produced. In one mode, a first pulse of a first voltage and a second pulse of a second voltage are sen... | 02/19/2008 |
| 7315661 | Directional interpolation method using DCT information and related device The invention provides a method for interpolating a pixel within an image. The image has a plurality of pixels arranged in a matrix format. The method includes detecting if there is an edge in a block of the image according to a Discrete Cosine Transform (DCT) data ... | 01/01/2008 |
| 7315931 | Method for managing an external memory of a microprocessor A method for managing an external memory of a microprocessor so that the external memory only contains one copy of a common area. By providing an address translator, mapping the page and the address of the common area of the page pointed by a microprocessor to the p... | 01/01/2008 |
| 7313068 | Apparatus and method for automatic power control An apparatus and method for automatic power control is disclosed. An optical recording apparatus utilizes a low-speed, peak-hold circuit to obtain and output a maximum of a front photodiode output signal during a predetermined window or plurality of windows of a tot... | 12/25/2007 |
| 7299341 | Embedded system with instruction prefetching device, and method for fetching instructions in embedded systems In a method for fetching instructions in an embedded system, a predicted one of a set of the instructions stored in a memory device is fetched and is subsequently stored in an instruction buffer when a system bus is in a data access phase. When a processor generates... | 11/20/2007 |
| 7272093 | Apparatus for controlling an optical disk drive by calculating a target frequency of a DPLL signal A control circuit for an optical disk drive includes a frequency detector, a phase detector, a low pass filter, a voltage-controlled oscillator (VCO), and a controller. The frequency detector and the phase detector both receive an eight-to-fourteen modulation (EFM) ... | 09/18/2007 |
| 7271649 | DC offset calibration apparatus A DC offset calibration device for calibrating a DC offset of an output signal of a gain stage, the DC offset calibration device includes: a digital-to-analog converter (DAC) electrically connected to the gain stage for generating an offset current according to the ... | 09/18/2007 |
| 7269288 | Apparatus for parallel calculation of prediction bits in a spatially predicted coded block pattern and method thereof A storage device stores rows of bits including a D0 bit, an X0 bit, an X1 bit, a Y0 bit, a Y1 bit and a spatially predicted coded block pattern having an A0 bit, an A1 bit, an A2 bit, and an A3 bit. A fi... | 09/11/2007 |
| 7266134 | Transmission circuit for a digital communication system A transmission circuit for realizing a rate adaptation layer of a digital communication system. The transmission circuit includes a processor and a format conversion circuit. The processor is capable of managing transmission rates of input and output digital signals... | 09/04/2007 |
| 7262644 | Method and apparatus for switching frequency of a system clock A system clock switching apparatus, which includes a clock source for providing a reference clock signal; a frequency divider electrically connected to the clock source for dividing the reference clock signal to produce a frequency-divided signal and a system clock ... | 08/28/2007 |
| 7251706 | System and method for updating firmware in a non-volatile memory without using a processor A processing system connected to an apparatus includes a non-volatile memory (NVM) for storing firmware needed by the processing system; and an NVM control interface capable of writing and reading data stored in the NVM; wherein the NVM control interface reads a pre... | 07/31/2007 |
| 7236027 | Jitter-resistive delay lock loop circuit for locking delayed clock and method thereof A delay lock loop circuit for delaying a reference clock to lock a delayed clock. The delay lock loop circuit includes a clock divider for dividing a frequency of the reference clock by N to generate a frequency-divided clock, a programmable delay circuit electrical... | 06/26/2007 |
| 7234041 | Embedded system with instruction prefetching device, and method for fetching instructions in embedded systems In a method for fetching instructions in an embedded system, a predicted one of a set of the instructions stored in a memory device is fetched and is subsequently stored in an instruction buffer when a system bus is in a data access phase. When a processor generates... | 06/19/2007 |
| 7224295 | System and method for modulation and demodulation using code subset conversion The present invention provides a method and system for converting an input code into an output code. The method includes: determining a plurality of input code subsets of the input code; converting the input code subsets into a plurality of output code subsets, resp... | 05/29/2007 |
| 7205847 | Phase locked loop for controlling an optical recording device and method thereof A phase locked loop (PLL) system for generating a reference clock to write recording data on an optical medium includes a clock generator generating the reference clock according to a phase difference between the reference signal and a first frequency-divided signal... | 04/17/2007 |
| 7203614 | Method and calibration system for IQ DC offset and imbalance calibration by utilizing analytic formulas to quickly determined desired compensation values A method for determining a target in-phase DC offset compensation value and a target quadrature-phase DC offset compensation value used for compensating DC offset of a database. The method includes: inputting a reference signal into a database which stores a plurali... | 04/10/2007 |
| 7203050 | NPN Darlington ESD protection circuit An electrostatic discharge protection (ESD) circuit includes an NPN Darlington circuit and an n-type metal oxide semiconductor (NMOS) transistor. The drain of NMOS transistor is connected to the input end of the NPN Darlington circuit. The source of NMOS transistor ... | 04/10/2007 |
