Bizarre Patents
Wearable Device For Feeding and Observing Birds and Other Flying Animals
A device for feeding and observing flying animals comprising a hat, a support mounted on the hat and extending outward from the hat, and a feeder mounted on the support.
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| Number | Title | Issue Date |
| 8183849 | Calibration apparatus and calibration method thereof A calibration apparatus includes: a first circuit arranged for generating a reference voltage with respect to a first circuit element according to a reference current flowing to the first circuit element, a second circuit arranged for generating an output voltage ac... | 05/22/2012 |
| 8175012 | Decoding/encoding method for booting from a NAND flash and system thereof A decoding method for booting from a NAND Flash including a booting page storing a plurality of copies of NAND booting information and a plurality of corresponding parities, each parity generated by an predetermined error correction code (ECC) bit number. The decodi... | 05/08/2012 |
| 8174441 | Configurable calculating circuit and receiver having a plurality of configurable calculating circuits A configurable calculating circuit includes a multiplexer, a mixer and an accumulator. The multiplexer is for receiving input signals including at least a first and a second input signals, and selectively outputting at least one of the input signals. The mixer is fo... | 05/08/2012 |
| 8174300 | Clock generator, pulse generator utilizing the clock generator, and methods thereof A clock generator for generating a target clock signal, comprising: a control circuit, receiving a reference clock signal, and for generating a clock enable signal and a delay selecting signal according to the reference clock signal; a delay module, coupled to the c... | 05/08/2012 |
| 8171335 | Clock timing calibration circuit and clock timing calibration method for calibrating phase difference between different clock signals and related analog-to-digital conversion system using the same A clock timing calibration circuit includes a clock timing adjusting unit and a calibration control unit. The clock timing adjusting unit is for receiving an incoming reference clock signal and selectively adjusting the received reference clock signal to generate a ... | 05/01/2012 |
| 8169248 | Signal processing circuit and signal processing method A signal processing circuit includes: a phase modulating path arranged to adjust a phase component of an input signal to generate an adjusted phase component such that a phase difference of the input signal falls within a target phase difference range; and an amplit... | 05/01/2012 |
| 8166369 | Method for error processing in optical disk memories A method of correcting and detecting errors in a sector of data stored in a DVD format is provided. The method includes: calculating an initial error detection value for data within the sector, performing an error correction operation on the data within the sector a... | 04/24/2012 |
| 8160137 | Image data compression apparatus for referring to at least one characteristic value threshold to select target compression result from candidate compression results of one block and related method thereof An exemplary image data compression apparatus includes a compression circuit, a characteristic value extracting circuit, and a selecting circuit. The compression circuit is utilized for applying a plurality of different compression approaches to a first block, and a... | 04/17/2012 |
| 8155455 | Image capturing system and method thereof An image capturing system comprises a storage device and a transcoder module coupled to the storage device. The storage device stores image data of a captured still image compressed by a first coding format configured. The transcoder module transcodes the image data... | 04/10/2012 |
| 8154847 | Capacitor structure A capacitor structure is disclosed. The capacitor structure includes at least a D1+ first-level array. The D1+ first-level array comprises three first D1+ conductive pieces and a second D1+ conductive piece. Two of the fir... | 04/10/2012 |
| 8154330 | Delay line calibration mechanism and related multi-clock signal generator A delay line calibration mechanism includes a delay line, a phase detector, and a controller. The delay line receives an input pulse, a calibration pulse, a first delay selection signal, and a second delay selection signal, delays the input pulse for a delay period ... | 04/10/2012 |
| 8149907 | Adaptive equalization apparatus with equalization parameter setting adaptively adjusted according to edges of equalizer output monitored in real-time manner and related method thereof An adaptive equalization apparatus is provided. The adaptive equalization apparatus includes an equalizer, a monitor circuit, and a control circuit. The equalizer receives a first signal, and equalizes the first signal according to an equalization parameter setting ... | 04/03/2012 |
| 8149022 | Digital delay line based frequency synthesizer A frequency synthesizer is disclosed. The frequency synthesizer includes a period control word generator, a delta-sigma modulator, and a delay line unit. The period control word generator generates a period control word. The delta-sigma modulator receives the period... | 04/03/2012 |
| 8145971 | Data processing systems and methods for processing digital data with low density parity check matrix A data processing system for processing digital data with a low density parity check (LDPC) matrix includes: a storage device for storing a plurality of indices representing a plurality of shifting numbers, where the LDPC matrix comprises an array of elements, and a... | 03/27/2012 |
| 8144552 | TE signal polarity determining system and related method thereof A tracking error (TE) signal polarity determining method, comprising: (a) obtaining a wobble related signal and a TE signal from an optical pick-up unit accessing an optical disc; (b) determining an accessing direction; and (c) determining if an original polarity of... | 03/27/2012 |
| 8143869 | Voltage reference circuit with fast enable and disable capabilities A circuit for providing an output voltage substantially equal to a reference voltage includes: a low drop-out (LDO) regulator coupled to the reference voltage for producing the output voltage at an output terminal; a reference current source having a first end and a... | 03/27/2012 |
| 8140041 | Tunable capacitive device with linearization technique employed therein One exemplary tunable capacitive device includes a first tunable capacitive element, a first coupling capacitive element, a first coupling resistive element, and a first specific capacitive element. The first tunable capacitive element has a first node coupled to a ... | 03/20/2012 |
| 8138616 | Bond pad structure A bond pad structure of an integrated circuit includes a conductive pad disposed on a first dielectric layer, a first conductive block formed in a second dielectric layer below the first dielectric layer and electrically connected to the conductive pad through a fir... | 03/20/2012 |
| 8125557 | Image evaluation method, image capturing method and digital camera thereof for evaluating and capturing images according to composition of the images An image evaluation method for a digital camera includes analyzing the composition of an image for obtaining a characteristic of the composition of the image, computing an ideal characteristic value, a real characteristic value, and a difference value between the id... | 02/28/2012 |
| 8122445 | Processing system capable of downloading firmware code and being tested at same site during MP phase A processing system capable of downloading a firmware code and being tested at the same site during a mass production phase includes: a processor for performing operations of the processing system, where the processor has a plurality of terminals as communication te... | 02/21/2012 |
| 8120067 | Power and ground routing of integrated circuit devices with improved IR drop and chip performance An integrated circuit chip includes a semiconductor substrate having thereon a plurality of IMD layers and first conductive layers embedded in the IMD layers; a first insulating layer overlying the IMD layers and the first conductive layers; a plurality of first pow... | 02/21/2012 |
| 8099644 | Encoders and methods for encoding digital data with low-density parity check matrix A method for encoding digital data with a low-density parity check (LDPC) matrix includes: indirectly storing a non-regular portion of the LDPC matrix by storing a plurality of indices corresponding to a plurality of non-zero sub-matrices of the non-regular portion,... | 01/17/2012 |
| 8094836 | Multi-channel decoding systems capable of reducing noise and methods thereof A multi-channel decoding method includes: receiving an input signal to generate a first channel output signal and a second channel output signal, wherein the input signal is mixed with a specific clock signal; and gradually changing an amplitude of the specific cloc... | 01/10/2012 |
| 8093722 | System-in-package with fan-out WLCSP A system-in-package includes a package carrier; a first semiconductor die having a die face and a die edge, the first semiconductor die being assembled face-down to a chip side of the package carrier; a second semiconductor die mounted alongside of the first semicon... | 01/10/2012 |
| 8085087 | Switched capacitor circuit capable of minimizing clock feedthrough effect and having low phase noise and method thereof A switched capacitor circuit includes a positive side capacitor coupled to a first positive side node; a first positive side switch element for selectively coupling the first positive side node to a second node according to a first control signal; and a precharge ci... | 12/27/2011 |
| 8084853 | Semiconductor flip chip package utilizing wire bonding for net switching This invention provides a semiconductor flip chip package including a carrier substrate and a flip chip mounted on the carrier substrate. The flip chip comprises a first input/output (I/O) pad and a second I/O pad on an active surface of the flip chip, wherein a swi... | 12/27/2011 |
| 8082582 | Authorization system of navigation device and associated authorization method An authorization system of a navigation device includes a first identification (ID) module and a second ID module. The first ID module is arranged to perform authorization for a first portion of the navigation device, and the second ID module is arranged to perform ... | 12/20/2011 |
| 8081936 | Method for tuning a digital compensation filter within a transmitter, and associated digital compensation filter and associated calibration circuit A method for tuning a digital compensation filter within a transmitter includes: obtaining at least one loop gain calibration result by performing loop gain calibration based upon signals of at least a portion of the transmitter, and obtaining at least one resistanc... | 12/20/2011 |
| 8077569 | Methods and devices for controlling access to an optical disc A device for controlling access to an optical disc includes a control word calculator and a numerically controlled oscillator (NCO). The control word calculator is arranged to calculate a control word corresponding to a radius where the optical disc is accessed. In ... | 12/13/2011 |
| 8077564 | Method for improving readability of an optical disc, and associated optical storage apparatus A method for improving readability of an optical disc includes: changing a first control parameter of an optical storage apparatus that accesses the optical disc and obtaining a plurality of associated values of an index corresponding to the readability of the optic... | 12/13/2011 |
| 8077086 | Methods and apparatus for obtaining GNSS time in a GNSS receiver A method and apparatus for obtaining Global navigation Satellite System (GNSS) time in a GNSS receiver are provided. The following steps are included: obtaining a time relationship between a first clock signal and the received GNSS time; obtaining a first clock valu... | 12/13/2011 |
| 8077085 | Methods for processing correction messages, correcting position measurements of GNSS receiver, and related apparatuses Methods and apparatuses for processing correction messages in a GNSS receiver are provided. One of the proposed methods includes providing a first storage unit; receiving a plurality of correction messages from at least one data sources, wherein a plurality of assis... | 12/13/2011 |
| 8073418 | Receiving systems and methods for audio processing A receiving system for audio processing includes a first demodulation unit and a second demodulation unit. The first demodulation unit is utilized for receiving an audio signal and generating a first demodulated audio signal. The second demodulation unit is utilized... | 12/06/2011 |
| 8073406 | Amplitude modulation circuit in polar transmitter and method for calibrating amplitude offset in polar transmitter An amplitude modulation circuit in a polar transmitter and a method for calibrating amplitude offset in the polar transmitter are provided. The amplitude modulation circuit includes a digital-to-analog converter (DAC), a low pass filter (LPF), a gm stage, and a cali... | 12/06/2011 |
| 8072004 | Power and ground routing of integrated circuit devices with improved IR drop and chip performance An integrated circuit chip includes a semiconductor substrate having thereon a plurality of inter-metal dielectric (IMD) layers and a plurality of first conductive layers embedded in respective the plurality of IMD layers, wherein the first conductive layers compris... | 12/06/2011 |
| 8065563 | System for booting from a non-XIP memory utilizing a boot engine that does not have ECC capabilities during booting A booting system includes: a non-XIP memory, for storing a plurality of booting images, wherein the booting images comprise a source image and a plurality of duplicates of the source image; an XIP memory, coupled to the non-XIP memory; and a code shadowing module, c... | 11/22/2011 |
| 8058720 | Semiconductor package A semiconductor package includes a die pad; a semiconductor die mounted on the die pad; a plurality of leads in a first horizontal plane disposed along peripheral edges of the die pad; a ground bar downset from the first horizontal plane to a second horizontal plane... | 11/15/2011 |
| 8050129 | E-fuse apparatus for controlling reference voltage required for programming/reading e-fuse macro in an integrated circuit via switch device in the same integrated circuit An electrically programmable fuse (e-fuse) apparatus includes an e-fuse macro and a switch device. The e-fuse macro is disposed in an integrated circuit, and has a plurality of e-fuse units. The switch device is disposed in the integrated circuit, and has an output ... | 11/01/2011 |
| 8049820 | Video processing circuits and methods using same buffer for video decoder and cross color suppressor A video processing circuit capable of processing a composite signal and a non-composite signal, includes: a line buffer; a frame buffer; a video decoder for decoding the composite signal by utilizing the line buffer and the frame buffer as temporary buffers of the v... | 11/01/2011 |
| 8049321 | Semiconductor device assembly and method thereof A semiconductor device assembly includes a first semiconductor die, a second semiconductor die, at least one semiconductor package component or another semiconductor die, a first conductive element and a second conductive element. The first semiconductor die include... | 11/01/2011 |
