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| Number | Title | Issue Date |
| 8183106 | Apparatus and associated method for making a floating gate memory device with buried diffusion dielectric structures and increased gate coupling ratio A method for fabricating a floating gate memory device comprises using self-aligned process for formation of a fourth poly layer over a partial gate structure that does not require an additional photolithographic step. Accordingly, enhanced device reliability can be... | 05/22/2012 |
| 8178407 | Systems and methods for a high density, compact memory array A memory array comprising vertical memory cells does not require any isolation layers between cells. Thus, a very compact, high density memory array can be achieved. Each memory cell in the memory array is configured to store 4 bits of data per cell. Multi-level cha... | 05/15/2012 |
| 8149610 | Nonvolatile memory device A memory device comprises an array of memory cells each capable of storing multiple bits of data. Each memory cell includes a programmable transistor in series with a resistance switching device. The transistor is switchable between a plurality of different threshol... | 04/03/2012 |
| 8085086 | Non-volatile memory device and charge pump circuit for the same A charge pump apparatus comprises a plurality of charge pump stages, including a first stage, and one or more succeeding stages. The charge pump stages each include a respective output node. Each output node is connected to charge boosting circuitry and to precharge... | 12/27/2011 |
| 8084791 | Non-volatile memory device including nitrogen pocket implants and methods for making the same In a non-volatile memory structure, the source/drain regions are surrounded by a nitrogen-doped region. As a result, an interface between the substrate and the charge trapping layer above the nitrogen-doped region is passivated by a plurality of nitrogen atoms. The ... | 12/27/2011 |
| 8076778 | Method for preventing Al-Cu bottom damage using TiN liner A semiconductor device and related method for fabricating the same include providing a stacked structure including an insulating base layer and lower and upper barrier layers with a conductive layer in between, etching the stacked structure to provide a plurality of... | 12/13/2011 |
| 8017480 | Apparatus and associated method for making a floating gate cell in a virtual ground array A method for fabricating a floating gate memory device comprises using thin buried diffusion regions with increased encroachment by a buried diffusion oxide layer into the buried diffusion layer and underneath the tunnel oxide under the floating gate. Further, the f... | 09/13/2011 |
| 8003519 | Systems and methods for back end of line processing of semiconductor circuits A BEOL manufacturing process for forming a via process between two metal lines on a semiconductor wafer comprises depositing a portion of a first metal adhesion layer within a patterned via hole, followed by a cooling step. The cooling step is then followed by forma... | 08/23/2011 |
| 7982262 | NAND memory device with inversion bit lines A NAND based memory device uses inversion bit lines in order to eliminate the need for implanted bit lines. As a result, the cell size can be reduced, which can provide greater densities in smaller packaging. In another aspect, a method for fabricating a NAND based ... | 07/19/2011 |
| 7968861 | Phase change memory element Thin-film phase-change memories having small phase-change switching volume formed by overlapping thin films. Exemplary embodiments include a phase-change memory element, including a first phase change layer having a resistance, a second phase change layer having a r... | 06/28/2011 |
| 7952213 | Overlay mark arrangement for reducing overlay shift An overlay mark arrangement for reducing the asymmetric profile and an overlay shift during an integrated circuit manufacturing process is disclosed. In one embodiment, the overlay mark arrangement may comprise a first mark, a second mark and a stress releasing mean... | 05/31/2011 |
| 7947607 | Apparatus and associated method for making a virtual ground array structure that uses inversion bit lines A virtual ground array structure uses inversion bit lines in order to eliminate the need for implanted bit lines. As a result, the cell size can be reduced, which can provide greater densities and smaller packaging. ... | 05/24/2011 |
| 7938972 | Fabrication method of electronic device A fabrication method of an electronic device is provided. First, a substrate is provided. Then, a patterned amorphous carbon (α-C) layer is formed on the substrate and exposes part of the substrate. Next, a first α-C layer covering the patterned α-C layer and par... | 05/10/2011 |
| 7932507 | Current constricting phase change memory element structure A layer of nanoparticles having a dimension on the order of 10 nm is employed to form a current constricting layer or as a hardmask for forming a current constricting layer from an underlying insulator layer. The nanoparticles are preferably self-aligning and/or sel... | 04/26/2011 |
| 7879706 | Memory and manufacturing method thereof A memory having isolated dual memory cells is provided. A first isolation wall and a second isolation wall are separately disposed between a source and a drain on a substrate. An isolation bottom layer and a polysilicon layer are orderly disposed on the substrate be... | 02/01/2011 |
| 7868313 | Phase change memory device and method of manufacture A phase change memory control ring lower electrode is disclosed. The lower electrode includes an outer ring electrode in thermal contact with a phase change memory element, an inner seed layer disposed within the outer ring electrode and in contact with the phase ch... | 01/11/2011 |
| 7835178 | Apparatus and method for detecting word line leakage in memory devices Some embodiments of the present invention provide a memory device including a first memory array having a first word line and a comparator circuit having a first terminal coupled to a reference voltage and a second terminal coupled to a first switch selectively coup... | 11/16/2010 |
| 7824991 | Method for nitridation of the interface between a dielectric and a substrate in a MOS device A MOSFET fabrication process comprises nitridation of the dielectric silicon interface so that silicon-dangling bonds are connected with nitrogen atoms creating silicon—nitrogen bonds, which are stronger than silicon-hydrogen bonds. A tunnel dielectric is formed o... | 11/02/2010 |
| 7773416 | Single poly, multi-bit non-volatile memory device and methods for operating the same A non-volatile memory device comprises a substrate with a dielectric layer formed thereon. A control gate is formed on the dielectric layer, as are two floating gates, one on either side of the control gate. Accordingly, the non-volatile memory device can be constru... | 08/10/2010 |
| 7759721 | Single poly non-volatile memory device with inversion diffusion regions and methods for operating the same A non-volatile memory device comprises a substrate with the dielectric layer formed thereon. A control gate and a floating gate are then formed on top of the dielectric layer. Accordingly, a non-volatile memory device can be constructed using a single poly process t... | 07/20/2010 |
| 7755129 | Systems and methods for memory structure comprising a PPROM and an embedded flash memory A memory structure that combines embedded flash memory and PPROM. The PPROM can be used as a memory structure. The flash memory can be used, e.g., as air replacement cells or back up memory, or additional memory cells. The PPROM cells are stacked on top of the flash... | 07/13/2010 |
| 7754611 | Chemical mechanical polishing process A chemical mechanical polishing method is disclosed. The method includes forming a film on a wafer having at least one trench structure thereon; polishing the surface of the film by providing a polishing composition to provide a first polished surface; rinsing the f... | 07/13/2010 |
| 7723778 | 2-bit assisted charge memory device and method for making the same An Assisted Charge (AC) Memory cell comprises a transistor that includes, for example, a p-type substrate with an n+ source region and an n+ drain region implanted on the p-type substrate. A gate electrode can be formed over the substrate and portions of the source ... | 05/25/2010 |
| 7723240 | Methods of low temperature oxidation A method for forming a dielectric is provided. The method includes providing a substrate having a silicon-containing semiconductor layer within a process chamber. The process chamber is capable of ionizing a process precursor to a plasma comprising an oxygen-contain... | 05/25/2010 |
| 7723229 | Process of forming a self-aligned contact in a semiconductor device A process is implemented to form a contact opening in a semiconductor device that includes a gate electrode on a substrate, a spacer on a sidewall of the gate electrode and a dielectric material covering the gate electrode. The process comprises forming a photoresis... | 05/25/2010 |
| 7718491 | Method for making a NAND Memory device with inversion bit lines A NAND based memory device uses inversion bit lines in order to eliminate the need for implanted bit lines. As a result, the cell size can be reduced, which can provide greater densities in smaller packaging. In another aspect, a method for fabricating a NAND based ... | 05/18/2010 |
| 7718348 | Photolithography process and photomask structure implemented in a photolithography process In a photolithography process, a photoresist layer is formed on a substrate. A photomask is aligned over the substrate to transfer pattern images defined in the photomask on the substrate. The photomask includes first and second patterns of different light transmiss... | 05/18/2010 |
| 7696884 | Systems and methods for enhancing the magnetic coupling in a wireless communication system An RFID system comprises an intermediate device that includes a first and second antenna coils connected together in a close loop format. The coils are formed on a flexible substrate that can be folded around a magnetic flux blocker such that one loop is on side of ... | 04/13/2010 |
| 7684234 | Methods and apparatus for thermally assisted programming of a magnetic memory device A magnetic memory device comprises a magnetic memory cell that includes a pinned layer and a free layer separated from the pinned layer by an insulating layer. The magnetic memory device also comprises a thermal plate in contact with the free layer. The magnetic mem... | 03/23/2010 |
| 7655970 | Single poly non-volatile memory device with inversion diffusion regions and methods for operating the same A non-volatile memory device comprises a substrate with the dielectric layer formed thereon. A control gate and a floating gate are then formed next to each other on top of the dielectric layer separated by a gap. Accordingly, a non-volatile memory device can be con... | 02/02/2010 |
| 7643258 | Methods and apparatus for electrostatic discharge protection in a semiconductor circuit An ESD protection circuit is adapted for an integrated circuit with a first power source and a second power source. The ESD protection circuit comprises a first silicon controlled rectifier (SCR), and in some embodiments a second silicon controlled rectifier, and a ... | 01/05/2010 |
| 7638393 | Non-volatile memory device including nitrogen pocket implants and methods for making the same In a non-volatile memory structure, the source/drain regions are surrounded by a nitrogen-doped region. As a result, an interface between the substrate and the charge trapping layer above the nitrogen-doped region is passivated by a plurality of nitrogen atoms. The ... | 12/29/2009 |
| 7629265 | Cleaning method for use in semiconductor device fabrication A novel cleaning method for preventing defects and particles resulting from post tungsten etch back or tungsten chemical mechanical polish is provided. The cleaning method comprises providing a stack structure of a semiconductor device including a tungsten plug in a... | 12/08/2009 |
| 7608886 | Systems and methods for a high density, compact memory array A memory array comprising vertical memory cells does not require any isolation layers between cells. Thus, a very compact, high density memory array can be achieved. Each memory cell in the memory array is configured to store 4 bits of data per cell. Multi level cha... | 10/27/2009 |
| 7596030 | Method for improving memory device cycling endurance by providing additional pulse A method for improving the cycle endurance of a memory device during a memory cell programming operation includes applying a first negative bias pulse measured from a gate to a drain of the memory device at a level sufficient to induce hot hole injection into a nitr... | 09/29/2009 |
| 7580280 | Method and apparatus for a non-volatile memory device with reduced program disturb A non-volatile memory device includes a plurality of power control circuits interfaced via a single Y multiplexer with an array of memory cells. The multiple power control circuits provide multiple pre-charge paths configured to pre-charge the drain node of a target... | 08/25/2009 |
| 7575990 | Method of forming self-aligned contacts and local interconnects A method of forming a plurality of self-aligned contacts of a core region and local interconnect openings of a peripheral region of a semiconductor device is disclosed. A plurality of gate-structures are formed on the core and peripheral regions of a semiconductor s... | 08/18/2009 |
| 7563690 | Method for forming shallow trench isolation region A method for forming a shallow trench isolation (STI) structure is provided. A pad oxide layer and a nitride silicon layer are formed on a provided substrate sequentially. The pad oxide layer, the nitride silicon layer and the substrate are then etched to form a tre... | 07/21/2009 |
| 7553755 | Method for symmetric deposition of metal layer A method for symmetric deposition of metal layer over a metal layer registration key comprises using MOCVD to form the metal layer. Once the symmetric metal layer is formed, a metal layer registration key can be accurately detected and the metal layer registration k... | 06/30/2009 |
| 7544618 | Two-step chemical mechanical polishing process A chemical mechanical polishing method is disclosed. The method includes forming a film on a wafer having at least one trench structure thereon; polishing the surface of the film by providing a polishing composition to provide a first polished surface; rinsing the f... | 06/09/2009 |
