Assignee: Macronix International Co, Ltd

Location: Hsin-Chu, TW
No. of patents: 220

Number	Title	Issue Date
7463512	Memory element with reduced-current phase change element A memory device having a reduced-thickness phase change film is described along with methods for manufacture. The device includes an electrode element, in electrical contact with a phase change layer. The latter element is formed from a memory material having at lea...	12/09/2008
7462925	Method and apparatus for stacking electrical components using via to provide interconnection An efficient chip stacking structure is described that includes a leadframe having two surfaces to each of which can be attached stacks of chips. A chip stack can be formed by placing a chip active surface on a back surface of another chip. Electrical connections be...	12/09/2008
7463530	Operating method of non-volatile memory device An operating method of non-volatile memory device is provided. The device includes memory cells having a semiconductor substrate, a stack layer, and source and drain regions disposed below a surface of the substrate and separated by a channel region. The stack layer...	12/09/2008
7463539	Method for burst mode, bit line charge transfer and memory using the same A memory device operates according to a method for reading includes pre-charging a first set of selected bit lines to a pre-charge voltage and sensing data from the cells coupled to the first set of selected bit lines. Then, residual charge is transferred from the f...	12/09/2008
7459798	Overlay mark An overlay mark is provided. A first material layer is formed on a substrate, and then a first trench serving as a trench type outer mark is formed in the first material layer. The first trench is partially filled with the first deposition layer. A second material i...	12/02/2008
7459717	Phase change memory cell and manufacturing method A phase change memory cell includes first and second electrodes having generally coplanar surfaces spaced apart by a gap and a phase change bridge electrically coupling the first and second electrodes. The phase change bridge may extend over the generally coplanar s...	12/02/2008
7456460	Phase change memory element and method of making the same Thin-film phase-change memories having small phase-change switching volume formed by overlapping thing films. Exemplary embodiments include a phase-change memory element, including a first phase change layer having a resistance, a second phase change layer having a ...	11/25/2008
7456421	Vertical side wall active pin structures in a phase change memory and manufacturing methods A programmable resistor memory, such as a phase change memory, with a memory element comprising narrow vertical side wall active pins is described. The side wall active pins comprise a programmable resistive material, such as a phase change material. In a first aspe...	11/25/2008
7453734	Method and apparatus for fast programming of memory Methods and apparatuses are disclosed for programming a page of nonvolatile memory cells across multiple nonvolatile memory cells accessed by multiple word lines. ...	11/18/2008
7453714	Over-driven access method and device for ferroelectric memory An over-driven access method and device for ferroelectric memory. When accessing the data stored in a ferroelectric memory, the invention further provides an over-driven current to slightly reduce/raise the voltages in bit lines BL and BL′ to further enlarge the v...	11/18/2008
7450423	Methods of operating non-volatile memory cells having an oxide/nitride multilayer insulating structure A method of operating a memory cell by applying a positive voltage to the gate sufficient to cause hole tunneling from the gate toward the charge storage layer is disclosed. The method is applied to a memory cell including a semiconductor layer having at least two s...	11/11/2008
7450411	Phase change memory device and manufacturing method A phase change memory device comprises a photolithographically formed phase change memory cell having first and second electrodes and a phase change bridge positioned between and electrically coupling the opposed sides of the electrodes to one another. The phase cha...	11/11/2008
7449792	Pattern registration mark designs for use in photolithography and methods of using the same Pattern registration marks which include: a substrate and an upper material layer disposed above the substrate; an outer trench formed in the upper material layer, the outer trench having an outer trench width; an inner trench formed in the upper material layer, the...	11/11/2008
7449710	Vacuum jacket for phase change memory element A memory device including a phase change element and a vacuum jacket. The device includes a first electrode element; a phase change element in contact with the first electrode element; an upper electrode element in contact with the phase change element; a bit line e...	11/11/2008
7447068	Method for programming a multilevel memory A method for programming a MLC memory is provided. The MLC memory has a number of bits, and each bit has a number of programmed states. Each programmed state has a first PV level. The method comprises programming the bits of the memory having a Vt level lower than t...	11/04/2008
7444682	Security memory device and method for making same A security memory device includes a memory cell array that stores a plurality of contents, including a mine, which is stored as a portion of the plurality of contents. The mine is triggered when it is accessed, typically such that the mine erases the memory contents...	10/28/2008
7443753	Memory structure, programming method and reading method therefor, and memory control circuit thereof The memory structure improves a sensing accuracy of memory cells by dividing the main array into a number of memory units and sensing memory cells of each memory units with an appropriate set of reference currents. Each of the memory units corresponds to a reference...	10/28/2008
7442610	Low thermal budget fabrication method for a mask read only memory device A low thermal budget fabrication method for a mask ROM is described. The method includes providing a substrate having a gate oxide layer thereon. A first conductive layer is formed on the gate oxide layer. A plurality of bit lines is formed in the substrate. A secon...	10/28/2008
7442603	Self-aligned structure and method for confining a melting point in a resistor random access memory A process in the manufacturing of a resistor random access memory with a confined melting area for switching a phase change in the programmable resistive memory. The process initially formed a pillar comprising a substrate body, a first conductive material overlying...	10/28/2008
7440328	Operation methods for a non-volatile memory cell in an array A method of reducing gate disturb in a charge-trapping layer memory cell by applying different Vpass voltages to different sides of a selected wordline. A higher Vpass voltage is used to pass higher source/drain voltage and a lower Vpass voltage is used to pass a lo...	10/21/2008
7440315	Method, apparatus and computer program product for stepped reset programming process on programmable resistive memory cell A method, system and computer program product for resetting a phase change memory cell having a memory cell threshold voltage is disclosed. The method includes reading a resistance of the memory cell. If the resistance is larger than a chosen resistance, the resetti...	10/21/2008
7439085	Method and apparatus for electroluminescence Methods and apparatuses for causing electroluminescence with charge trapping structures are disclosed. Various embodiments relate to methods and apparatuses for causing electroluminescence with charge carriers of one type provided to the charge trapping structure by...	10/21/2008
7435681	Methods of etching stacks having metal layers and hard mask layers Methods which comprise: providing a stack to be etched, the stack comprising a metal interconnect layer disposed above a substrate, a barrier layer disposed above the metal interconnect layer, a hard mask layer disposed on the barrier layer, and a patterning layer d...	10/14/2008
7435648	Methods of trench and contact formation in memory cells Methods of contact formation and memory arrays formed using such methods, which methods include providing a memory array having a plurality of bit lines disposed below a surface of a semiconductor substrate and a plurality of word lines disposed above the surface of...	10/14/2008
7435512	Photolithography process and photomask structure implemented in a photolithography process In a photolithography process, a photoresist layer is formed on a substrate. A photomask is aligned over the substrate to transfer pattern images defined in the photomask on the substrate. The photomask includes first and second patterns of different light transmiss...	10/14/2008
7433247	Method and circuit for reading fuse cells in a nonvolatile memory during power-up A method and circuit are described for ensuring a properly operational power-up read of fuse cells in a nonvolatile memory by selecting predefined data for loading in a portion of a fuse memory and matching the reading of the predefined data during power-up with the...	10/07/2008
7433238	Method of programming memory cell A method of programming a memory cell is described. First, a first programming operation is performed to inject electrons into a nitride layer adjacent to a side of a drain. The first programming operation includes applying a first gate voltage to a gate, applying a...	10/07/2008
7432739	Low voltage complementary metal oxide semiconductor process tri-state buffer A low voltage complementary metal oxide semiconductor (CMOS) process tri-state buffer includes a logic device, a biasing device and a switch device. The logic device receives an input signal and an enable signal and generates a first control signal and a second cont...	10/07/2008
7432605	Overlay mark, method for forming the same and application thereof An overlay mark for checking the alignment accuracy between a lower layer and a lithography process for defining an upper layer is described, including a part of the lower layer having two first x-directional trenches, two first y-directional trenches, two second x-...	10/07/2008
7432206	Self-aligned manufacturing method, and manufacturing method for thin film fuse phase change ram A method for manufacturing a self aligned narrow structure over a wider structure based on mask trimming. A method for manufacturing a memory device comprises forming an electrode layer on a substrate which comprises circuitry made using front-end-of-line procedures...	10/07/2008
7433226	Method, apparatus and computer program product for read before programming process on multiple programmable resistive memory cell A method, system and computer program product for programming a plurality of programmable resistive memory cells is disclosed. The method comprises executing a first process to program input data, including setting up bias voltages on bit lines and word lines on the...	10/07/2008
7427519	Method of detecting end point of plasma etching process A method of detecting an end point of a plasma etching process for etching a first layer on a second layer is described, the first layer producing a first etching product and the second layer a second etching product. Time-dependent intensity [Ij=1 to m(t...	09/23/2008
7426140	Bandgap engineered split gate memory Memory cells comprising: a semiconductor substrate having a source region and a drain region disposed below a surface of the substrate and separated by a channel region; a tunnel dielectric structure disposed above the channel region, the tunnel dielectric structure...	09/16/2008
7426139	Dynamic program and read adjustment for multi-level cell memory array A method for operating a multi-level cell (“MLC”) memory array of an integrated circuit (“IC”) programs first data into a first plurality of MLCs in the MLC memory array at a first programming level. Threshold voltages for the first plurality of MLCs are sen...	09/16/2008
7423913	Structures and methods for enhancing erase uniformity in a nitride read-only memory array A virtual ground nitride read-only memory array has a matrix of nitride read-only memory cells in which during an erase operation the non-erasing side of nitride read-only memory cells are connected to a common node for enhancing the erase uniformity of the nitride ...	09/09/2008
7423300	Single-mask phase change memory element A memory device. An array of memory elements is formed on a semiconductor chip. A parallel array of word lines extends in a first direction, connecting each memory element to a data source, and a parallel array of bit lines extends in a second direction, connecting ...	09/09/2008
7420242	Stacked bit line dual word line nonvolatile memory An arrangement of nonvolatile memory devices, having at least one memory device level stacked level by level above a semiconductor substrate, each memory level comprising an oxide layer substantially disposed above a semiconductor substrate, a plurality of word line...	09/02/2008
7419868	Gated diode nonvolatile memory process A gated diode nonvolatile memory cell with a charge storage structure includes a diode structure with an additional gate terminal. Various embodiments may include or exclude a diffusion barrier structure between the diode nodes. Example embodiments include the indiv...	09/02/2008
7413834	Photomask with alignment marks for the current layer A photomask with alignment marks for the current layer is provided with four edges. The photomask includes main patterns, an inter-scribe lane pattern sited between the main patterns, an extra-scribe lane pattern only sited on the three edges of the photomask, a fir...	08/19/2008
7414889	Structure and method of sub-gate and architectures employing bandgap engineered SONOS devices A bandgap engineered SONOS device structure for design with various AND architectures to perform a source side injection programming method. The BE-SONOS device structure comprises a spacer oxide disposed between a control gate overlaying an oxide-nitride-oxide-nitr...	08/19/2008

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Assignee: Macronix International Co, Ltd