Assignee: MIPS Technologies, Inc.

Location: Sunnyvale, CA
No. of patents: 96

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Number	Title	Issue Date
8185879	External trace synchronization via periodic sampling A method for tracing a multi-tasking embedded pipelined processor includes executing compiled code including trace controls. Tracing is initiated when the execution of the compiled code is initiated. Tracing is stopped when execution of the compiled code is complete...	05/22/2012
8185717	Apparatus and method for profiling software performance on a processor with non-unique virtual addresses A system includes a processor with a memory map specifying a user mode region with virtual address translation by a memory management unit and a kernel mode region with direct virtual address translation. The processor executes an application in the user mode region...	05/22/2012
8181000	Method and apparatus for binding shadow registers to vectored interrupts A method and apparatus within a processing system is provided for associating shadow register sets with interrupt routines. The invention includes a vector generator that receives interrupts, and generates exception vectors to call interrupt routines that correspond...	05/15/2012
8151268	Multithreading microprocessor with optimized thread scheduler for increasing pipeline utilization efficiency A multithreading processor for concurrently executing multiple threads is provided. The processor includes an execution pipeline and a thread scheduler that dispatches instructions of the threads to the execution pipeline. The execution pipeline execution pipeline i...	04/03/2012
8151093	Software programmable hardware state machines The present invention provides software programmable hardware state machines to detect a cause of an error in a processor and prevent the error from occurring. In example embodiments, processors, systems and methods are provided to prevent an unwanted change in arch...	04/03/2012
8131941	Support for multiple coherence domains A number of coherence domains are maintained among the multitude of processing cores disposed in a microprocessor. A cache coherency manager defines the coherency relationships such that coherence traffic flows only among the processing cores that are defined as hav...	03/06/2012
8103987	System and method for managing the design and configuration of an integrated circuit semiconductor design A system and methods that facilitate the design process and minimize the time and effort required to complete the design and fabrication of an integrated circuits (IC) are described. The system and method utilize a plurality of repositories, rules engines and design...	01/24/2012
8081645	Context sharing between a streaming processing unit (SPU) and a packet management unit (PMU) in a packet processing environment A method for processing multiple data packets includes receiving from a network interface, at a packet management unit (PMU), a data packet for processing, and determining whether to store or drop the data packet. The method further includes queueing the data packet...	12/20/2011
8078846	Conditional move instruction formed into one decoded instruction to be graduated and another decoded instruction to be invalidated A conditional move instruction implemented in a processor by forming and processing two decoded instructions, and applications thereof. In an embodiment, the conditional move instruction specifies a first source operand, a second source operand, and a third operand ...	12/13/2011
8078840	Thread instruction fetch based on prioritized selection from plural round-robin outputs for different thread states A fetch director in a multithreaded microprocessor that concurrently executes instructions of N threads is disclosed. The N threads request to fetch instructions from an instruction cache. In a given selection cycle, some of the threads may not be requesting to fetc...	12/13/2011
8078806	Microprocessor with improved data stream prefetching A microprocessor coupled to a system memory by a bus includes an instruction decode unit that decodes an instruction that specifies a data stream in the system memory and a stream prefetch priority. The microprocessor also includes a load/store unit that generates l...	12/13/2011
8077734	Method and apparatus for predicting characteristics of incoming data packets to enable speculative processing to reduce processor latency A system for processing data packets in a data packet network has at least one input port for receiving data packets, at least one output port for sending out data packets, a processor for processing packet data, and a packet predictor for predicting a future packet...	12/13/2011
8074058	Providing extended precision in SIMD vector arithmetic operations The present invention provides extended precision in SIMD arithmetic operations in a processor having a register file and an accumulator. A first set of data elements and a second set of data elements are loaded into first and second vector registers, respectively. ...	12/06/2011
8069354	Power management for system having one or more integrated circuits Power management control software including power management policies is provided with those policies divided into observation code and response code. When predetermined execution points within the operating system 2 are reached or an application specific tas...	11/29/2011
8037253	Method and apparatus for global ordering to insure latency independent coherence A method and apparatus is described for insuring coherency between memories in a multi-agent system where the agents are interconnected by one or more fabrics. A global arbiter is used to segment coherency into three phases: request; snoop; and response, and to appl...	10/11/2011
8032734	Coprocessor load data queue for interfacing an out-of-order execution unit with an in-order coprocessor A coprocessor interface unit for interfacing a coprocessor to an out-of-order execution pipeline, and applications thereof. In an embodiment, the coprocessor interface unit includes an in-order instruction queue, a coprocessor load data queue, and a coprocessor stor...	10/04/2011
8024539	Virtual processor based security for on-chip memory, and applications thereof A processor-based method, system and apparatus to comprise a method, system and apparatus to access a memory location in an on-chip memory based on a virtual processing element identification associated with an instruction. The system comprises multiple virtual proc...	09/20/2011
8024393	Processor with improved accuracy for multiply-add operations Floating-point processors capable of performing multiply-add (Madd) operations and incorporating improved intermediate result handling capability. The floating-point processor includes a multiplier unit coupled to an adder unit. In a specific operating mode, the int...	09/20/2011
8001283	Efficient, scalable and high performance mechanism for handling IO requests A system, apparatus and method for managing input/output requests in a multi-processor system is disclosed. An IO coherence unit includes an IO request handler, a variable size transaction table, and an IO response handler. The size of the transaction table varies a...	08/16/2011
7961745	Bifurcated transaction selector supporting dynamic priorities in multi-port switch A bifurcated selector for transmitting transactions from a plurality of transaction queues out a port of a switch. A transaction scheduler selects transactions of the queues for transmission to a device coupled to the port. A policy manager enforces a scheduling pol...	06/14/2011
7926062	Interrupt and exception handling for multi-streaming digital processors A multi-streaming processor has a plurality of streams for streaming one or more instruction threads, a set of functional resources for processing instructions from streams, and interrupt handler logic. The logic detects and maps interrupts and exceptions to one or ...	04/12/2011
7925864	Method and apparatus for binding shadow registers to vectored interrupts A method and apparatus within a processing system is provided for associating shadow register sets with interrupt routines. The invention includes a vector generator that receives interrupts, and generates exception vectors to call interrupt routines that correspond...	04/12/2011
7925859	Three-tiered translation lookaside buffer hierarchy in a multithreading microprocessor A three-tiered TLB architecture in a multithreading processor that concurrently executes multiple instruction threads is provided. A macro-TLB caches address translation information for memory pages for all the threads. A micro-TLB caches the translation information...	04/12/2011
7917882	Automated digital circuit design tool that reduces or eliminates adverse timing constraints due to an inherent clock signal skew, and applications thereof The present invention provides an automated digital circuit design tool that reduces or eliminates adverse timing constraints due to an inherent clock signal skew, and applications thereof. In an embodiment, an automated design tool according to the invention genera...	03/29/2011
7911952	Interface with credit-based flow control and sustained bus signals An interface between electronic devices uses a credit-based flow protocol with sustained bus signals. An initiating device waits for credit to issue a command to a target device. When credit is available, the initiating device issues the command to the target device...	03/22/2011
7900207	Interrupt and exception handling for multi-streaming digital processors A multi-streaming processor has a plurality of streams for streaming one or more instruction threads, a set of functional resources for processing instructions from streams, and interrupt handler logic. The logic detects and maps interrupts and exceptions to one or ...	03/01/2011
7899993	Microprocessor having a power-saving instruction cache way predictor and instruction replacement scheme Microprocessor having a power-saving instruction cache way predictor and instruction replacement scheme. In one embodiment, the processor includes a multi-way set associative cache, a way predictor, a policy counter, and a cache refill circuit. The policy counter pr...	03/01/2011
7895423	Method for extracting fields from packets having fields spread over more than one register Systems and methods that allow for extracting a field from data stored in a pair of registers using two instructions. A first instruction extracts any part of the field from a first register designated as a first source register, and executes a second instruction ex...	02/22/2011
7886150	System debug and trace system and method, and applications thereof An embedded system or system on chip (SoC) includes a secure JTAG system and method to provide secure on-chip control, capture, and export of on chip information in an embedded environment to a probe. In one embodiment, the system comprises encryption logic associat...	02/08/2011
7886129	Configurable co-processor interface A configurable coprocessor interface between a central processing unit (CPU) and a coprocessor is provided. The coprocessor interface has an instruction transfer signal group for transferring different instruction types from the CPU to the coprocessor, sequentially ...	02/08/2011
7849297	Software emulation of directed exceptions in a multithreading processor A multithreading microprocessor has a plurality of thread contexts (TCs) each including sufficient state, such as general purpose registers and program counter, to execute a separate thread of execution as one of a plurality of symmetric processors controlled by a m...	12/07/2010
7877481	Method and apparatus for overflowing data packets to a software-controlled memory when they do not fit into a hardware-controlled memory A system for managing packets incoming to a data router has a local packet memory (LPM) mapped into pre-configured memory units, to store packets for processing, an external packet memory (EPM), a first storage system to store packets in the LPM, and a second storag...	01/25/2011
7873820	Processor utilizing a loop buffer to reduce power consumption The present invention provides processing systems, apparatuses, and methods that reduce power consumption with the use of a loop buffer. In an embodiment, an instruction fetch unit of a processor initially provides instructions from an instruction cache to an execut...	01/18/2011
7873810	Microprocessor instruction using address index values to enable access of a virtual buffer in circular fashion A modular subtraction instruction for execution on a microprocessor having at least one register. The instruction includes opcode bits for designating the instruction and operand bits for designating at least one register storing an offset index, a decrement value, ...	01/18/2011
7870553	Symmetric multiprocessor operating system for execution on non-independent lightweight thread contexts A multiprocessing system is disclosed. The system includes a multithreading microprocessor having a plurality of thread contexts (TCs), a translation lookaside buffer (TLB) shared by the plurality of TCs, and an instruction scheduler, coupled to the plurality of TCs...	01/11/2011
7865647	Efficient resource arbitration Resource requests are allocated by storing resource requests in a queue slots in a queue. A token is associated with one of the queue slots. During an arbitration cycle, the queue slot with the token is given the priority to the resource. If the queue slot with the ...	01/04/2011
7860911	Extended precision accumulator A multiply unit includes an extended precision accumulator. Microprocessor instructions are provided for manipulating portions of the extended precision accumulator including an instruction to move the contents of a portion of the extended accumulator to a general-p...	12/28/2010
7853777	Instruction/skid buffers in a multithreading microprocessor that store dispatched instructions to avoid re-fetching flushed instructions An apparatus for reducing instruction re-fetching in a multithreading processor configured to concurrently execute a plurality of threads is disclosed. The apparatus includes a buffer for each thread that stores fetched instructions of the thread, having an indicato...	12/14/2010
7840874	Speculative cache tag evaluation A cache tag comparison unit in a cache controller evaluates tag data and error correction codes to determine if there is a cache hit or miss. The cache tag comparison unit speculatively compares the tag data with the request tag without regard to error correction. T...	11/23/2010
7836450	Symmetric multiprocessor operating system for execution on non-independent lightweight thread contexts A multiprocessing system is disclosed. The system includes a multithreading microprocessor, including a plurality of thread contexts (TCs), each comprising a first control indicator for controlling whether the TC is exempt from servicing interrupt requests to an exc...	11/16/2010

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Assignee: MIPS Technologies, Inc.