Assignee: MICRON TECHNOLOGY, INC.

Location: Boise, ID
No. of patents: 3166

«First «Previous1 2 3 4 5 6 7 8 9 10 11 Next»Last»

Number	Title	Issue Date
8184492	Tri-state driver circuits having automatic high-impedance enabling Memories, driver circuits, and methods for generating an output signal in response to an input signal. One such driver circuit includes an input stage and an output stage. The input stage receives the input signal and provides a delayed input signal having a delay r...	05/22/2012
8184489	Level shifting circuit A level shifting circuit having an input and an output where the level shifting circuit is configured to receive a logical high level having a first voltage level at the input and to output a logical high level having a second voltage level at the output where the s...	05/22/2012
8184487	Modified read operation for non-volatile memory A method may comprise executing a read operation to access a memory array by performing a preactive command to include a row-address-write operation and a bitline precharge and column selection operation and performing an activate command including a column-address-...	05/22/2012
8184481	Memory devices and methods of their operation including selective compaction verify operations Memory devices and methods of their operation, where following an erasure of a string of memory cells, a selective compaction verify operation is performed on one or more, but less than all, of the memory cells of the string, and, if the selective compaction verify ...	05/22/2012
8184469	Stored multi-bit data characterized by multiple-dimensional memory states A method for enhancing data storage may comprise storing two or more bits in a memory cell, wherein the stored bits may be characterized by two or more independent variables based, at least in part, on physical properties of the memory cell. ...	05/22/2012
8184188	Methods and apparatus for high dynamic operation of a pixel cell A pixel circuit providing high dynamic operation, and methods of operating the pixel circuit providing for high dynamic operation. Methods include a lateral overflow and a double exposure mode, and a pixel output signal is determined according to whether a photosens...	05/22/2012
8183901	Delay locked loop circuit and method Delay locked loop circuits and methods are disclosed. In the embodiments, a delay locked loop may include a phase detector to detect a phase difference between a clock signal and a reference clock signal, and a charge pump that receives the detected phase difference...	05/22/2012
8183880	Devices and methods for driving a signal off an integrated circuit Embodiments of the present invention provide electronic devices, memory devices and methods of driving an on-chip signal off a chip. In one such embodiment, an on-chip signal and a second signal complementary to the on-chip signal are generated and provided to the t...	05/22/2012
8183625	NROM flash memory devices on ultrathin silicon An NROM flash memory cell is implemented in an ultra-thin silicon-on-insulator structure. In a planar device, the channel between the source/drain areas is normally fully depleted. An oxide layer provides an insulation layer between the source/drain areas and the ga...	05/22/2012
8183615	Memory cell with a vertically oriented transistor coupled to a digit line and method of forming the same A memory cell, array and device include an active area formed in a substrate with a vertical transistor including a first end disposed over a first portion of the active area. The vertical transistor is formed as an epitaxial post on the substrate surface, extends f...	05/22/2012
8183515	Pumps for CMOS imagers A pixel for an imaging device is described. The pixel includes a photosensitive device provided within a substrate for providing photo-generated charges, a circuit associated with the photosensitive device for providing at least one pixel output signal representativ...	05/22/2012
8183157	Method of forming capacitors, and methods of utilizing silicon dioxide-containing masking structures Some embodiments include methods of forming capacitors. Storage nodes are formed within a material. The storage nodes have sidewalls along the material. Some of the material is removed to expose portions of the sidewalls. The exposed portions of the sidewalls are co...	05/22/2012
8183154	Selective metal deposition over dielectric layers Selective deposition of metal over dielectric layers in a manner that minimizes or eliminates keyhole formation is provided. According to one embodiment, a dielectric target layer is formed over a substrate layer, wherein the target layer may be configured to allow ...	05/22/2012
8183151	Methods of forming conductive vias through substrates, and structures and assemblies resulting therefrom Methods of forming conductive elements on and in a substrate include forming a layer of conductive material over a surface of a substrate prior to forming a plurality of vias through the substrate from an opposing surface of the substrate to the layer of conductive ...	05/22/2012
8183138	Methods for forming nanodots and/or a patterned material during the formation of a semiconductor device Methods for forming nanodots and/or a patterned material are provided. One such method involves forming a first patterning material over a base. Blades of a nanoimprint lithography template are placed within the first patterning material, wherein the blades extend a...	05/22/2012
8183110	Memory cells, methods of forming dielectric materials, and methods of forming memory cells Some embodiments include memory cells. The memory cells may include a tunnel dielectric material, a charge-retaining region over the tunnel dielectric material, crystalline ultra-high k dielectric material over the charge-retaining region, and a control gate materia...	05/22/2012
8183085	High rate selective polymer growth on a substrate Method and systems provide growth of polymer structures at a high rate in a selective manner. In various embodiments, the method or system can expose the growth site to a polymer source and growing a polymer tube at a rate of at least 80 micrometer per hour at the g...	05/22/2012
8181086	Memory array error correction apparatus, systems, and methods Various embodiments include apparatus, methods, and systems that operate to extend the processes of reading, modifying, and writing data stored in or being provided to a memory array without interrupting a continual stream of data to be written into the memory array...	05/15/2012
8180995	Logical address offset in response to detecting a memory formatting operation The present disclosure includes methods, devices, and systems for a logical address offset. One method embodiment includes detecting a memory unit formatting operation. Subsequently, in response to detecting the formatting operation, the method includes inspecting f...	05/15/2012
8180974	System, apparatus, and method for modifying the order of memory accesses Systems and methods for controlling memory access operations are disclosed. The system may include one or more requestors performing requests to memory devices. Within a memory controller, a request queue receives requests from a requestor, a bank decoder determines...	05/15/2012
8180609	Jittery signal generation with discrete-time filtering The computer-implementable method allows for the fast creation of a multi-unit interval data signal suitable for simulation. The created signal represents the output of an otherwise ideal Discrete Time Filter (DTF) circuit, and the quick creation of the signal merel...	05/15/2012
8180150	Method and apparatus providing automatic color balancing for digital imaging systems Pixels from an image are sampled for gray world statistics. To avoid the effect of saturated regions, the pixels are pruned. If a predetermined percentage of the pixels are included in the gray world statistics, color channel gain is calculated and applied to the im...	05/15/2012
8179726	Method and apparatus for programming flash memory A method and apparatus that provides the ability to control programming pulses having different widths and/or voltages in a flash memory device. The widths and/or voltage levels of programming pulses are set to achieve programming of all memory cells of an array usi...	05/15/2012
8179725	Programming rate identification and control in a solid state memory Memory devices adapted to receive and transmit analog data signals representative of bit patterns of two or more bits facilitate increases in data transfer rates relative to devices communicating data signals indicative of individual bits. Programming of such memory...	05/15/2012
8179724	Sensing for memory read and program verify operations in a non-volatile memory device Methods for sensing in a memory device and a memory device are disclosed. In one such sensing method, a single read operation with multiple sense amplifier circuit comparisons to a reference threshold level are performed to determine a state of a selected memory cel...	05/15/2012
8179706	Method for modifying data more than once in a multi-level cell memory location within a memory array A method and apparatus for marking a block of multi-level memory cells for performance of a block management function by programming at least one bit in a lower page of the memory cell block such that a first logic state is stored in the at least one bit in the lowe...	05/15/2012
8179468	Integrated CMOS imager and microcontroller A method and apparatus providing a CMOS imager with an integrated controller on a common integrated circuit substrate. Also integrated on the common substrate are, a serializer circuit including a dynamic arbiter under the control of the microcontroller core and a s...	05/15/2012
8178984	Flip chip with interposer A device is disclosed which includes a die comprising an integrated circuit and an interposer that is coupled to the die, the interposer having a smaller footprint than that of the die. A method is disclosed which includes operatively coupling an interposer to a die...	05/15/2012
8178911	Semiconductor device having reduced sub-threshold leakage A semiconductor device fabricated in the semiconductor substrate includes a FinFET transistor having opposed source and drain pillars, and a fin interposed between the source and drain pillars. A cavity is formed in the semiconductor substrate extending at least par...	05/15/2012
8178413	Low-temperature grown high quality ultra-thin CoTiOgate dielectrics A gate oxide and method of fabricating a gate oxide that produces a more reliable and thinner equivalent oxide thickness than conventional SiO2 gate oxides are provided. Gate oxides formed from alloys such as cobalt-titanium are thermodynamically stable s...	05/15/2012
8178396	Methods for forming three-dimensional memory devices, and related structures Methods of forming semiconductor devices that include one or more arrays of memory devices in a three-dimensional arrangement, such as those that include forming a conductive contact in a dielectric material overlying a memory array, wherein a wafer bonding and clea...	05/15/2012
8177420	Apparatus and methods for temperature calibration and sensing Some embodiments include apparatus and methods having a first switch, a second switch, and a circuit coupled to the first and second switches. The first switch may be configured to switch between an on-state and an off-state based on a value of a first current flowi...	05/15/2012
8176547	System and method for controlling user access to an electronic device A system requires a user to enter a geometric pattern on an interface device to gain access to the system. After the correct geometric pattern is entered, a timer times a duration before an authenticating password is subsequently entered by the user. If the duration...	05/08/2012
8176371	Embedded processor Electronic apparatus, systems, and methods of operating and constructing the electronic apparatus and/or systems include an embedded processor disposed in a logic chip to direct, among other functions, self-testing of an electronic device structure in conjunction wi...	05/08/2012
8176232	Dedicated interface to factory program phase-change memories A nonvolatile memory device has a dedicated serial programming port to provide a data path to memory storage. A dedicated power pin supplies power for the programming port to receive data and provide storage in the nonvolatile memory while a power pin for normal dev...	05/08/2012
8174919	Apparatus and method for increasing data line noise tolerance Circuits and methods for improving noise tolerance in memories are disclosed such as those that include biasing a data line above a normal threshold voltage, either by providing a higher data line charge voltage with a voltage source, or by providing a higher data l...	05/08/2012
8174900	Wordline voltage transfer apparatus, systems, and methods The apparatus and systems described herein may comprise a plurality of memory cells coupled to a local wordline, and a wordline drive circuit that includes a regulator coupled to a plurality of pass transistors and a string driver. The regulator may comprise a regul...	05/08/2012
8174897	Programming in a memory device Methods for programming a memory device and memory devices are provided. According to at least one such method, a selected memory cell is programmed by a series of programming pulses. The series of programming pulses are configured in sets of programming pulses wher...	05/08/2012
8174893	Independent well bias management in a memory device Methods for programming a memory device, memory devices configured to perform the disclosed programming methods, and memory systems having a memory device configured to perform the disclosed programming methods, for example, are provided. According to at least one s...	05/08/2012
8174887	Adjusting for charge loss in a memory Memory and methods of operating a memory adjusting an output voltage of an analog storage device, such as a data cache capacitor holding a voltage level representative of data, in response to an estimated charge loss are useful for compensating for the effects of ch...	05/08/2012

«First «Previous1 2 3 4 5 6 7 8 9 10 11 Next»Last»

PatentStorm

Did You Know...

PatentStorm News

Assignee: MICRON TECHNOLOGY, INC.