Assignee: MEARS Technologies, Inc.

Location: Waltham, MA
No. of patents: 26

Number	Title	Issue Date
7928425	Semiconductor device including a metal-to-semiconductor superlattice interface layer and related methods A semiconductor device which may include a semiconductor layer, and a superlattice interface layer therebetween. The superlattice interface layer may include a plurality of stacked groups of layers. Each group of layers may include a plurality of stacked base semico...	04/19/2011
7880161	Multiple-wavelength opto-electronic device including a superlattice A multiple-wavelength opto-electronic device may include a substrate and a plurality of active optical devices carried by the substrate and operating at different respective wavelengths. Each optical device may include a superlattice comprising a plurality of stacke...	02/01/2011
7863066	Method for making a multiple-wavelength opto-electronic device including a superlattice A method for making a multiple-wavelength opto-electronic device which may include providing a substrates and forming a plurality of active optical devices to be carried by the substrate and operating at different respective wavelengths. Moreover, each optical devic...	01/04/2011
7812339	Method for making a semiconductor device including shallow trench isolation (STI) regions with maskless superlattice deposition following STI formation and related structures A semiconductor device may include a semiconductor substrate having a surface, a shallow trench isolation (STI) region in the semiconductor substrate and extending above the surface thereof, and a superlattice layer adjacent the surface of the semiconductor substrat...	10/12/2010
7781827	Semiconductor device with a vertical MOSFET including a superlattice and related methods A semiconductor device may include at least one vertical Metal Oxide Semiconductor Field Effect Transistor (MOSFET) on a substrate. The vertical MOSFET may include at least one superlattice including a plurality of laterally stacked groups of layers transverse to th...	08/24/2010
7718996	Semiconductor device comprising a lattice matching layer A semiconductor device may include a first monocrystalline layer comprising a first material having a first lattice constant. A second monocrystalline layer may include a second material having a second lattice constant different than the first lattice constant. The...	05/18/2010
7700447	Method for making a semiconductor device comprising a lattice matching layer A method for making a semiconductor device which may include forming a first monocrystalline layer comprising a first material having a first lattice constant, a second monocrystalline layer including a second material having a second lattice constant different than...	04/20/2010
7659539	Semiconductor device including a floating gate memory cell with a superlattice channel A semiconductor device may include a semiconductor substrate and at least one non-volatile memory cell. The at least one memory cell may include spaced apart source and drain regions, and a superlattice channel including a plurality of stacked groups of layers on th...	02/09/2010
7625767	Methods of making spintronic devices with constrained spintronic dopant A method is for making a spintronic device and may include forming at least one superlattice and at least one electrical contact coupled thereto, with the at least one superlattice including a plurality of groups of layers. Each group of layers may include a plurali...	12/01/2009
7612366	Semiconductor device including a strained superlattice layer above a stress layer A semiconductor device may include a stress layer and a strained superlattice layer above the stress layer and including a plurality of stacked groups of layers. More particularly, each group of layers of the strained superlattice layer may include a plurality of st...	11/03/2009
7598515	Semiconductor device including a strained superlattice and overlying stress layer and related methods A semiconductor device may include a strained superlattice layer including a plurality of stacked groups of layers, and a stress layer above the strained superlattice layer. Each group of layers of the strained superlattice layer may include a plurality of stacked b...	10/06/2009
7586165	Microelectromechanical systems (MEMS) device including a superlattice A microelectromechanical system (MEMS) device may include a substrate and at least one movable member supported by the substrate. The at least one movable member may include a superlattice including a plurality of stacked groups of layers with each group of layers o...	09/08/2009
7535041	Method for making a semiconductor device including regions of band-engineered semiconductor superlattice to reduce device-on resistance A method for making a semiconductor device which may include providing a substrate having a plurality of spaced apart superlattices therein, and forming source and drain regions in the substrate defining a channel region therebetween and with the plurality of spaced...	05/19/2009
7531850	Semiconductor device including a memory cell with a negative differential resistance (NDR) device A semiconductor device may include at least one memory cell comprising a negative differential resistance (NDR) device and a control gate coupled thereto. The NDR device may include a superlattice including a plurality of stacked groups of layers, with each group of...	05/12/2009
7531829	Semiconductor device including regions of band-engineered semiconductor superlattice to reduce device-on resistance A semiconductor device may include a substrate and spaced apart source and drain regions defining a channel region therebetween in the substrate. The substrate may have a plurality of spaced apart superlattices in the channel and/or drain regions. Each superlattice ...	05/12/2009
7531828	Semiconductor device including a strained superlattice between at least one pair of spaced apart stress regions A semiconductor device may include at least one pair of spaced apart stress regions, and a strained superlattice layer between the at least one pair of spaced apart stress regions and including a plurality of stacked groups of layers. Each group of layers of the str...	05/12/2009
7517702	Method for making an electronic device including a poled superlattice having a net electrical dipole moment A method for making an electronic device may include forming a poled superlattice comprising a plurality of stacked groups of layers and having a net electrical dipole moment. Each group of layers of the poled superlattice may include a plurality of stacked semicond...	04/14/2009
7514328	Method for making a semiconductor device including shallow trench isolation (STI) regions with a superlattice therebetween A method for making a semiconductor device may include forming a plurality of shallow trench isolation (STI) regions in a semiconductor substrate. Further, a plurality of layers may be deposited over the substrate to define respective superlattices over the substrat...	04/07/2009
7491587	Method for making a semiconductor device having a semiconductor-on-insulator (SOI) configuration and including a superlattice on a thin semiconductor layer A method for making a semiconductor device may include forming an insulating layer on a substrate, and forming a semiconductor layer on the insulating layer on a side thereof opposite the substrate. The method may further include forming a superlattice on the semico...	02/17/2009
7446334	Electronic device comprising active optical devices with an energy band engineered superlattice An electronic device may include first and second integrated circuits including respective first and second active optical devices establishing an optical communications link therebetween. The first active optical device may include a superlattice including a plural...	11/04/2008
7446002	Method for making a semiconductor device comprising a superlattice dielectric interface layer A method for making a semiconductor device may include forming a superlattice comprising a plurality of stacked groups of layers adjacent a substrate. Each group of layers of the superlattice may include a plurality of stacked base semiconductor monolayers defining ...	11/04/2008
7436026	Semiconductor device comprising a superlattice channel vertically stepped above source and drain regions A semiconductor device may include a semiconductor substrate and at least one metal oxide semiconductor field-effect transistor (MOSFET). The at least one MOSFET may include spaced apart source and drain regions in the semiconductor substrate, and a superlattice cha...	10/14/2008
7435988	Semiconductor device including a MOSFET having a band-engineered superlattice with a semiconductor cap layer providing a channel A semiconductor device may include a substrate and at least one MOSFET adjacent the substrate including a superlattice. The superlattice may include a plurality of stacked groups of layers and a semiconductor cap layer on an uppermost group of layers. Each group of ...	10/14/2008
7433729	Infrared biometric finger sensor including infrared antennas and associated methods A finger sensor may include an integrated circuit substrate for receiving a user's finger adjacent thereto, and a plurality of infrared sensing pixels on the substrate. Each infrared sensing pixel may include at least one temperature sensor, at least one infrared an...	10/07/2008
7432524	Integrated circuit comprising an active optical device having an energy band engineered superlattice An integrated circuit may include at least one active optical device including a superlattice including a plurality of stacked groups of layers. Each group of layers of the superlattice may include a plurality of stacked base semiconductor monolayers defining a base...	10/07/2008
7303948	Semiconductor device including MOSFET having band-engineered superlattice A semiconductor device includes a substrate, and at least one MOSFET adjacent the substrate. The MOSFET may include a superlattice channel that, in turn, includes a plurality of stacked groups of layers. The MOSFET may also include source and drain regions laterally...	12/04/2007

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Assignee: MEARS Technologies, Inc.