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...When G.G. Hubbard learned of his future son-in-law's invention, he called it "only a toy." His daughter was engaged to a young man named Alexander Graham Bell.
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| Number | Title | Issue Date |
| 8184288 | Method of depositing a silicon-containing material by utilizing a multi-step fill-in process in a deposition machine An advance process control (APC) system for a plasma process machine is provided, which includes at least an optical emission spectroscopy (OES) system and an APC analysis apparatus. The OES system is used for monitoring a testing object in the plasma process machin... | 05/22/2012 |
| 8183618 | Method for fabricating a charge trapping memory device A method for fabricating a charge trapping memory device includes providing a substrate; forming a first oxide layer on the substrate; forming a number of BD regions in the substrate; nitridizing the interface of the first oxide layer and the substrate via a process... | 05/22/2012 |
| 8183617 | Injection method with Schottky source/drain An injection method for non-volatile memory cells with a Schottky source and drain is described. Carrier injection efficiency is controlled by an interface characteristic of silicide and silicon. A Schottky barrier is modified by controlling an overlap of a gate and... | 05/22/2012 |
| 8183123 | Method of forming mark in IC-fabricating process A method of forming a mark in an IC fabricating process is described. Two parts of the mark each including a plurality of linear patterns are respectively defined by two exposure steps that either belong to two lithography processes respectively or constitute a doub... | 05/22/2012 |
| 8178405 | Resistor random access memory cell device A memory cell device has a bottom electrode and a top electrode, a plug of memory material in contact with the bottom electrode, and a cup-shaped conductive member having a rim that contacts the top electrode and an opening in the bottom that contacts the memory mat... | 05/15/2012 |
| 8178388 | Programmable resistive RAM and manufacturing method Integrated circuit nonvolatile memory uses programmable resistive elements. In some examples, conductive structures such as electrodes are prepared, and the programmable resistive elements are laid upon the prepared electrodes. This prevents contamination of the pro... | 05/15/2012 |
| 8178387 | Methods for reducing recrystallization time for a phase change material A method for reducing recrystallization time for a phase change material of a memory cell element in conjunction with the manufacture of a memory cell device can be carried out as follows. A phase change material, a buffer layer material and a cladding layer materia... | 05/15/2012 |
| 8178386 | Phase change memory cell array with self-converged bottom electrode and method for manufacturing An array of phase change memory cells is manufactured by forming a separation layer over an array of contacts, forming a patterning layer on the separation layer and forming an array of mask openings in the patterning layer using lithographic process. Etch masks are... | 05/15/2012 |
| 8176395 | Memory module and writing and reading method thereof A writing method of a memory module comprises temporarily storing a piece of 2m-byte data as p characters, wherein each character comprises q bits, and m, p and q are positive integers; rearranging the 2m-byte data to obtain K symbols, wherein ... | 05/08/2012 |
| 8176373 | Pre-code device, and pre-code system and pre-coding method thereof A pre-code device includes firstly memory circuit, an address decoder, and an alternative logic circuit. The first memory circuit includes a number of memory blocks and at east a replacing block. The memory blocks are pointed by a number of respective physical addre... | 05/08/2012 |
| 8174924 | Power saving method and circuit thereof for a semiconductor memory A power saving method for a semiconductor memory is provided. The power saving method for a semiconductor memory including the steps of receiving a plurality of address codes, each of which has a first part code and a second part code; and activating a first boost p... | 05/08/2012 |
| 8174904 | Memory array and method of operating one of a plurality of memory cells An embodiment of the invention provides a memory array including a plurality of bit lines, a plurality of memory cells and a device. Each of the plurality of memory cells has a first node, a second node and a third node, wherein the third node is coupled to one of t... | 05/08/2012 |
| 8174898 | Sense amplifier and data sensing method thereof A data sensing method for sensing data stored in first and second memory cells includes the steps of: setting a first voltage according to a bit-line voltage corresponding to the first memory cell in response to an enabled level of a first clock signal; providing th... | 05/08/2012 |
| 8174289 | Level shifter and level shifting method thereof A level shifter includes a first level-switching device and a second level-switching device. The first level-switching device includes a first switch device, a second switch device, a first control switch and a third switch device. The first switch device is for rec... | 05/08/2012 |
| 8173987 | Integrated circuit 3D phase change memory array and manufacturing method A 3D phase change memory device is based on an array of electrode pillars and a plurality of electrode planes that intersect the electrode pillars at interface regions that include memory elements that comprise a programmable phase change memory element and a thresh... | 05/08/2012 |
| 8169835 | Charge trapping memory cell having bandgap engineered tunneling structure with oxynitride isolation layer A band gap engineered, charge trapping memory cell includes a charge storage structure including a trapping layer. a blocking layer, and a dielectric tunneling structure including a thin tunneling layer, a thin bandgap offset layer and a thin isolation layer compris... | 05/01/2012 |
| 8168538 | Buried silicide structure and method for making Methods for manufacturing buried silicide lines are described herein, along with high density stacked memory structures. A method for manufacturing an integrated circuit as described herein includes forming a semiconductor body comprising silicon. A plurality of tre... | 05/01/2012 |
| 8164958 | Memory apparatus and method for operating the same The invention provides a method for reading a first data storage of a memory cell. The method comprises sensing a first current of the memory cell by applying a first bit line voltage on the memory cell. When the first current is larger than a first reference curren... | 04/24/2012 |
| 8164953 | Memory and boundary searching method thereof A memory and an operating method thereof are provided therein. When searching a boundary of a threshold voltage distribution of the memory, data errors resulted from tail bits of the memory would be corrected. Therefore, a sensing window could be broader, and the bo... | 04/24/2012 |
| 8164146 | Substrate symmetrical silicide source/drain surrounding gate transistor Field effect transistors described herein include first and second terminals vertically separated by a channel region. The first and second terminals comprise first and second silicide elements respectively. The first silicide element prevents the migration of carri... | 04/24/2012 |
| 8164112 | Electostatic discharge protection circuit coupled on I/O pad An I/O pad ESD protection circuit is composed of a SCR circuit, a first diode, a second diode, and an anti-latch-up circuit. The SCR circuit has a first connection terminal and a second connection terminal, respectively coupled to the I/O pad and the ground voltage,... | 04/24/2012 |
| 8158965 | Heating center PCRAM structure and methods for making Memory devices are described along with manufacturing methods. A memory device as described herein includes a bottom electrode and a first phase change layer comprising a first phase change material on the bottom electrode. A resistive heater comprising a heater mat... | 04/17/2012 |
| 8158963 | Programmable resistive RAM and manufacturing method Programmable resistive RAM cells have a resistance that depends on the size of the contacts. Manufacturing methods and integrated circuits for lowered contact resistance are disclosed that have contacts of reduced size. ... | 04/17/2012 |
| 8154705 | Method of defining patterns in small pitch and corresponding exposure system A method of defining patterns in a small pitch is described. A substrate having a target layer thereon is provided, and two laterally separate reflective structures with two opposite sidewalls are formed over the target layer. A photoresist layer is formed over the ... | 04/10/2012 |
| 8154128 | 3D integrated circuit layer interconnect A three-dimensional 3D interconnect structure with a small footprint is described, useful for connection from above to levels of circuit structures in a multi-level device. Also, an efficient and low cost method for manufacturing the 3D interconnect structure is pro... | 04/10/2012 |
| 8153491 | Non-volatile memory semiconductor device having an oxide-nitride-oxide (ONO) top dielectric layer A non-volatile memory (NVM) cell includes a silicon substrate having a main surface, a source region in a portion of the silicon substrate, a drain region in a portion of the silicon substrate, and a well region disposed in a portion of the silicon substrate between... | 04/10/2012 |
| 8153485 | Method for fabricating memory A method for fabricating a memory is described. Word lines are provided in a first direction. Bit lines are provided in a second direction. A top electrode is formed connecting to a corresponding word line. A bottom electrode is formed connecting to a corresponding ... | 04/10/2012 |
| 8149628 | Operating method of non-volatile memory device A non-volatile memory device includes memory cells having a semiconductor substrate, a stack layer, and source and drain regions disposed below a surface of the substrate and separated by a channel region. The stack layer includes an insulating layer disposed on the... | 04/03/2012 |
| 8149627 | Current sink system based on sample and hold for source side sensing Source-side sensing techniques described herein determine the data value stored in a memory cell based on the difference in current between the read current from the source terminal of the memory cell and a sink current drawn from the read current. The sink current ... | 04/03/2012 |
| 8149624 | Method and apparatus for reducing read disturb in memory Various aspects of a NAND memory include have multiple versions of a high threshold voltage distribution—a version with a reduced maximum, and another version. The version with a reduced maximum has a reduced word line pass voltage. ... | 04/03/2012 |
| 8148051 | Method and system for manufacturing openings on semiconductor devices A method and system to form openings comprises an exposure apparatus and a mask to selectively expose a semiconductor substrate to a radiation source to transfer assist feature patterns and primary feature patterns to a photosensitive layer of the substrate. A heati... | 04/03/2012 |
| 8143665 | Memory array and method for manufacturing and operating the same The invention provides a memory array. The memory array comprises a substrate, a plurality of word lines, a charge trapping structure, a plurality of trench channels and a plurality of bit lines. The word lines are located over the substrate and the word lines are p... | 03/27/2012 |
| 8143089 | Self-align planerized bottom electrode phase change memory and manufacturing method A method is described for self-aligning a bottom electrode in a phase change random access memory PCRAM device where a top electrode serves as a mask for self-aligning etching of the bottom electrode. The bottom electrode has a top surface that is planarized by chem... | 03/27/2012 |
| 8139425 | Voltage regulation method and memory applying thereof A voltage regulating method applied to a memory to regulate a word line voltage corresponding to a set of memory cells of the memory includes the following steps. Firstly, a first value, which is for indicating an amount of data having a specific data value in a set... | 03/20/2012 |
| 8139416 | Operation methods for memory cell and array for reducing punch through leakage A method for programming a first memory cell in a memory array. In a specific embodiment, each memory cell has a drain, a source, a channel, and a control gate overlying a charge storage material and the channel. The source of the first memory cell is coupled to the... | 03/20/2012 |
| 8139393 | Method and apparatus for non-volatile multi-bit memory A memory device that selectably exhibits first and second logic levels. A first conductive material has a first surface with a first memory layer formed thereon, and a second conductive material has a second surface with a second memory layer formed thereon. A conne... | 03/20/2012 |
| 8138540 | Trench type non-volatile memory having three storage locations in one memory cell A non-volatile memory. The non-volatile memory comprises a substrate, a conductive layer, a charge storage layer, several first doped regions and several second doped regions. The substrate has a plurality of trenches formed therein. The conductive layer is located ... | 03/20/2012 |
| 8135896 | Serial peripheral interface and method for data transmission A serial peripheral interface of an integrated circuit including multiple pins and a clock pin is provided. The pins are coupled to the integrated circuit for transmitting an instruction, an address or a read out data. The clock pin is coupled to the integrated circ... | 03/13/2012 |
| 8134865 | Operating method of electrical pulse voltage for RRAM application Metal-oxide based memory devices and methods for operating and manufacturing such devices are described herein. A method for manufacturing a memory device as described herein comprises forming a metal-oxide memory element, and applying an activating energy to the me... | 03/13/2012 |
| 8134857 | Methods for high speed reading operation of phase change memory and device employing same Phase change based memory devices and methods for operating described herein overcome the performance limitations of slow set speeds and long recovery times commonly associated with phase change memory devices, enabling high speed operation and extending their usefu... | 03/13/2012 |
