Did You Know...
...that the Slinky toy was the result of a failed attempt by engineer Richard James to produce an antivibration device for ship instruments? His goal was to develop a spring that would instantaneously counterbalance the wave motion that rocks a ship at sea. Instead, he developed the Slinky.
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| Number | Title | Issue Date |
| 6697362 | Distributed switch memory architecture A distributed memory switch system for transmitting packets from source ports to destination ports, comprising: a plurality of ports including a source port and a destination port wherein a packet is transmitted from the source port to the destination por... | 02/24/2004 |
| 6584145 | Sample rate converter A converter or a resampler used in a digital communication system converts a first digital signal representing an analog signal into a second digital signal representing the same analog signal. The converter includes a converter filter and a timing circui... | 06/24/2003 |
| 6584109 | Automatic speed switching repeater A network repeater having automatic speed switching capability. The repeater includes a first repeater logic for connecting devices operating at the first rate to a first backplane, a second repeater logic for connecting devices operating at the second ra... | 06/24/2003 |
| 6577677 | Method and apparatus for analog bias current optimization An analog bias current optimization circuitry in a transceiver of a data communication system is capable of controlling the amount of a bias current of each of analog circuits. The analog bias current optimization circuitry generates a signal pattern whic... | 06/10/2003 |
| 6577695 | Emulating narrow band phase-locked loop behavior on a wide band phase-locked loop A phase-locked loop circuit for providing a tightly controlled capture range for locking an output signal to a data signal, while also providing a wide frequency capture range for initially pulling the output signal within this narrow, predetermined frequ... | 06/10/2003 |
| 6566908 | Pulse width distortion correction logic level converter A pulse width distortion correction logic level converter converts differential logic while preserving the pulse width of the original signal. The converter converts a differential input signal to a single-ended signal having a same pulse width as the dif... | 05/20/2003 |
| 6552580 | Bias technique for operating point control in multistage circuits A multistage analog circuit for independently controlling a bias current in each stage of the multistage analog circuit having an input stage, an intermediate stage, and an output stage, includes a first current source which controls the input stage of th... | 04/22/2003 |
| 6535565 | Receiver rate converter phase calculation apparatus and method A communication system includes a timing circuit which generates phase conversion information from a transmitter to transfer data from a first clock domain to a second clock domain, and a receive phase calculation circuit which utilizes the phase informat... | 03/18/2003 |
| 6535567 | Method and apparatus for suppression of jitter in data transmission systems A jitter suppression apparatus in a data transmission system includes a phase detector circuit to determine a plurality of phase errors between sync pulses of a data line and sync pulses of a reference line, and an adapted phase error offset circuit, coup... | 03/18/2003 |
| 6529563 | Method and apparatus for providing a self-sustaining precision voltage and current feedback biasing loop A method and apparatus for providing a self-sustaining precise voltage and current feedback biasing loop. The present invention provides a circuit for initially biasing the bandgap and master bias current generator at startup. The feedback biasing loop ha... | 03/04/2003 |
| 6516185 | Automatic gain control and offset correction A direct conversion type transceiver system incorporates an offset correction and automatic gain control system. The automatic gain control system includes an amplifier amplifying a baseband signal which is directly converted from a received incoming RF s... | 02/04/2003 |
| 6472918 | Self-referencing slicer method and apparatus for high-accuracy clock duty cycle generation A system and method for regulating the duty cycle of a digital clock signal derived from an oscillator signal. The oscillator signal is DC-biased to a DC value representing an average DC value of an ideal digital clock signal having a 50% duty cycle. The ... | 10/29/2002 |
| 6469547 | Offset window detector An offset window detector that senses the sum of two signals and compares the result to a reference voltage for attenuating an offset voltage and producing a desired gain. The primary design issues of the detector is to achieve a very low voltage offset a... | 10/22/2002 |
| 6430287 | Combined parallel adaptive equalizer/echo canceller A combined, parallel adaptive equalizer/echo canceller is disclosed. The equalizer/canceller receives at least one input signal which is split into n taps. The n taps are multiplied by corresponding n tap coefficients to produce n tap output signals. The ... | 08/06/2002 |
| 6417655 | Common mode bias voltage generator A common mode bias voltage generator apparatus and method includes a plurality of MOSFET-based transistors and a plurality of resistors configured and arranged to provide a half of a supply voltage with a predetermined low output impedance while using rel... | 07/09/2002 |
| 6404810 | Activation method in data transceivers An activation method for adaptive equalization in a data transceiver including a plurality of adaptive filters wherein the adaptive filters are adapted with a first type of adaptation method to obtain initial convergence of the adaptive filters during an ... | 06/11/2002 |
| 6396356 | Linearization scheme for voltage controlled oscillator A VCO system for equalizing a positive frequency deviation and a negative frequency deviation by using two varactors is described. The VCO system includes an active circuit and an oscillating circuit. The active circuit includes a first input, a second in... | 05/28/2002 |
| 6369658 | Single-ended to differential transconductor A conversion circuit in a transceiver system is capable of converting a single-ended input voltage signal to balanced differential output signals. An input voltage signal can be referenced to the ground (zero voltage) GND and can travel both above and bel... | 04/09/2002 |
| 6342799 | Error correcting programmable pulse generator The invention relates in general to error correcting programmable pulse generator, and more particularly to a programmable pulse generator that removes errors due to manufacturing tolerances, power supply variation, and temperature. A method of modifying ... | 01/29/2002 |
| 6341148 | Method and apparatus for minimizing transient sampling fluctuations upon transition between modes of communication The present invention provides a transceiver which does not lose synchronization upon a transition from a non-precoded communication mode to a precoded communication mode and minimizes phase drift. A transceiver unit outputs a signal representing the phas... | 01/22/2002 |
| 6313685 | Offset cancelled integrator An offset integrator and method are provided to induce integrator leakage while simultaneously latching and canceling its own offset. The method includes combining a first and second input signals with a part of the output signal of a different polarity t... | 11/06/2001 |
| 6304136 | Reduced noise sensitivity, high performance FM demodulator circuit and method An FM demodulator circuit with reduced sensitivity to noise and performance nearly identical to theoretical predictions. The FM demodulator is a time sampled detector for binary shift key (BFSK) modulated signals. Its inputs are an in-phase and a quadratu... | 10/16/2001 |
| 6300752 | Common mode bias voltage generator A common mode bias voltage generator apparatus and method includes a plurality of MOSFET-based transistors and a plurality of resistors configured and arranged to provide a half of a supply voltage with a predetermined low output impedance while using rel... | 10/09/2001 |
| 6292161 | Multiple display blink scheme for integrated circuit with application sense A system operable with any number of different display truth table schemes. The system allows a user to select the truth table scheme and a driver circuit is used to drive either a single or pair of display elements. A binary application select detects a ... | 09/18/2001 |
| 6285659 | Automatic protocol selection mechanism A network device automatically detects the best protocol a network will support. The network device includes a driver for transmitting data, a receiver for receiving data, and a port operationally coupled to the driver and receiver. The network device fur... | 09/04/2001 |
| 6272640 | Method and apparatus employing an invalid symbol security jam for communications network security A security device for use in communications network devices, such as multi-port repeaters, in local area networks to prevent eavesdropping by overwriting the data with an invalid symbol in the data communication packets transmitted to all unintended trans... | 08/07/2001 |
| 6249557 | Apparatus and method for performing timing recovery A timing recovery circuit is disclosed that prevents phase error over-compensation. The timing recovery circuit includes a phase scanner for determining when phase error over-compensation has occurred and generating a signal for preventing dual phase comp... | 06/19/2001 |
| 6229855 | Adaptive transmitter for digital transmission A method for controlling the power and/or frequency output of a digital data network's transmitters is described. The method controls the transmitter power and/or frequency output by using line loss information as well as the noise margin at both the cent... | 05/08/2001 |
| 6229466 | Digital calibration method and apparatus for multi-bit delta-sigma D/A converter A system and method for calibrating a multi-bit feedback quantizer in a delta-sigma modulation system. A digital data pattern corresponding to a particular DAC code of a multi-bit digital-to-analog converter is transmitted in the transmit channel, where t... | 05/08/2001 |
| 6215335 | Nonoverlapping phased, resettable, peak detector A peak detector that compares an input signal to a first reference voltage to produce a maximum sample signal, and compares the input signal to a second reference voltage to produce a minimum sample signal, wherein the maximum and minimum sample signals p... | 04/10/2001 |
| 6198700 | Method and apparatus for retiming test signals A test signal retiming circuit that captures an input signal to produce a first output signal and generates a second output signal in response to the first output signal and a predetermined reference signal. The second output signal is resistant to an inp... | 03/06/2001 |
| 6188739 | Modified third order phase-locked loop A phase-locked loop circuit is disclosed which exhibits a wide capture range and a low quality factor (Q) to prevent ringing and improve stability without adding area, increasing power consumption or increasing noise levels. The phase-locked loop includes... | 02/13/2001 |
| 6175248 | Pulse width distortion correction logic level converter A pulse width distortion correction logic level converter converts differential logic while preserving the pulse width of the original signal. The converter converts a differential input signal to a single-ended signal having a same pulse width as the dif... | 01/16/2001 |
| 6169729 | 200 Mbps PHY/MAC apparatus and method A 200 Mbps PHY/MAC combination for providing full duplex operation at 400 Mbps is disclosed. The PHY/MAC uses all 4 pairs of wire to create a single channel. A transmit and receive port of a physical layer device is connected to a first end of four pairs ... | 01/02/2001 |
| 6167082 | Adaptive equalizers and methods for carrying out equalization with a precoded transmitter Adaptive equalization methods and adaptive equalizers used with precoded systems dominated by intersymbol interference (ISI) monitor the output of a DFE and compare it to a reference for updating a precoder in response to the comparison. To accomplish thi... | 12/26/2000 |
| 6154464 | Physical layer device having a media independent interface for connecting to either media access control entitices or other physical layer devices A PHY having a media independent interface (MII) providing connections to a MAC or to another PHY is disclosed. The invention provides a mechanism for connecting a first PHY with a second PHY, wherein the PHY may act as the media access control side of th... | 11/28/2000 |
| 6154075 | Error correcting programmable pulse generator The invention relates in general to error correcting programmable pulse generator, and more particularly to a programmable pulse generator that removes errors due to manufacturing tolerances, power supply variation, and temperature. A method of modifying ... | 11/28/2000 |
| 6134570 | Method and apparatus for efficient implementation of a multirate LMS filter An efficient implementation of a multirate filter with delayed error feedback prevents an instruction processing rate requirement from increasing by performing interpolation and decimation in a LMS filter element at the same time. The multirate filter cal... | 10/17/2000 |
| 6127887 | High gain, impedance matching low noise RF amplifier circuit A low noise amplifier circuit provides high gain and an input impedance matching a source output impedance by combining two amplifiers having different operational characteristics in parallel. The amplifier circuit includes a first amplifier having an inp... | 10/03/2000 |
| 6121831 | Apparatus and method for removing offset in a gain circuit An offset-removing gain circuit where the detected offset is independent of the gain of the circuit. The gain circuit includes a differential amplifier transfer circuit with an input and a output, an integrator connected to the output of the differential ... | 09/19/2000 |
