Assignee: Lattice Semiconductor Corporation

Location: Hillsboro, OR
No. of patents: 443

Browse patents
Browse applications

«First «Previous1 2 3 4 5 6 7 8 9 10 11 Next»Last»

Number	Title	Issue Date
8169237	Comparator with jitter mitigation In one embodiment, a circuit such as a comparator circuit includes a differential stage adapted to receive a differential input signal and first and second diodes coupled to the differential stage. The first and second diodes are adapted to selectively switch on and...	05/01/2012
8165164	In-system reconfigurable circuit for mapping data words of different lengths A mapping circuit is provided for mapping first data words into frames of second data words, wherein the first and second data words are of different length. In addition, a de-mapping circuit is provided for de-mapping the frames of second data words into the first ...	04/24/2012
8164499	Shared-array multiple-output digital-to-analog converter In an exemplary decision-feedback equalizer (DFE) of a serializer/deserializer (SerDes) receiver, a single current mirror array is shared by multiple current digital-to-analog converter (IDAC) functions. The DFE has an initial amplifier stage that applies an initial...	04/24/2012
8138790	Latency measurements for wireless communications In one embodiment, a programmable logic device (PLD) includes a programmable fabric and hard logic coupled to the programmable fabric. The hard logic includes a timing measurement circuit adapted to measure latency of a data path between first and second points in t...	03/20/2012
8132040	Channel-to-channel deskew systems and methods Systems and methods are disclosed herein to provide channel-to-channel skew control in accordance with one or more embodiments of the present invention. For example in accordance with an embodiment, a method of adjusting skew between first and second channels includ...	03/06/2012
8122277	Clock distribution chip In one embodiment, a clock distribution chip includes a clock input adapted to receive an input clock signal, clock dividers each adapted to receive a clock signal based on the first input clock signal and to generate a divided clock signal, and programmable clock o...	02/21/2012
8112731	Congestion-driven placement systems and methods for programmable logic devices Techniques are provided for reducing signal congestion in programmable logic devices (PLDs). In one example, a computer-implemented method of reducing signal congestion in a configuration of a PLD includes mapping a plurality of circuit components of a circuit desig...	02/07/2012
8112656	Clock distribution chip In one embodiment, a clock distribution chip includes a first clock input adapted to receive a first single-ended input clock signal, a second clock input adapted to receive a second single-ended input clock signal, and input buffer circuitry coupled to the first an...	02/07/2012
8108754	Programmable logic device programming verification systems and methods In one embodiment, a method of verifying a programming operation of a programmable logic device includes storing in non-volatile memory within the programmable logic device configuration data and a pre-calculated code value based on the configuration data. The metho...	01/31/2012
8104009	Wire mapping for programmable logic devices A computer-implemented method of referencing wires of a routing graph of a programmable logic device (PLD). In one embodiment, the method includes mapping the first routing graph wire to a master wire; mapping the first master wire to master switch; identifying a se...	01/24/2012
8086986	Clock boosting systems and methods In one embodiment of the invention, a programmable logic device (PLD) includes logic blocks, registers corresponding to the logic blocks, and configuration memory adapted to store configuration data for configuring the PLD. Also included in the PLD is a general rout...	12/27/2011
8069431	Routing signals to pins of components in programmable logic devices Various techniques are provided for routing signals to pins of components of programmable logic devices (PLDs). In one example, a computer-implemented method of routing signals in a PLD includes routing a plurality of signals to pins of a component of the PLD. At le...	11/29/2011
8069329	Internally triggered reconfiguration of programmable logic devices Various techniques are described to provide an internally triggered reconfiguration of a programmable logic device (PLD). In one example, a PLD includes configuration memory adapted to store first configuration data to configure the PLD for its intended function. Th...	11/29/2011
8065574	Soft error detection logic testing systems and methods A programmable logic device, in accordance with one embodiment, includes a plurality of configuration memory cells, wherein at least one configuration memory cell is adapted to function as random access memory. Read/write circuitry writes to and reads from a corresp...	11/22/2011
8060784	Programmable logic device and methods for providing multi-boot configuration data support In one embodiment of the invention, a programmable logic device includes configuration memory and a controller. The controller can read a first bitstream from a first memory block of non-volatile memory and detect whether the first bitstream contains a valid preambl...	11/15/2011
8059470	Flash memory array with independently erasable sectors In one embodiment, an integrated circuit includes a flash memory array with at least first and second subarrays, or sectors, of memory cells. The subarrays have a set of shared bitlines and separate sets of word lines. A bitline driver circuit is coupled to the set ...	11/15/2011
8058898	Compression and decompression of configuration data using repeated data frames In one embodiment, a method of converting an uncompressed bitstream into a compressed bitstream for a programmable logic device (PLD) is disclosed. The method includes embedding a first data frame from the uncompressed bitstream into the compressed bitstream, wherei...	11/15/2011
8040159	Comparator with jitter mitigation In one example, a comparator circuit includes a differential stage adapted to receive a differential input signal. The comparator circuit includes first and second diodes coupled to the differential stage. The first and second diodes are adapted to selectively switc...	10/18/2011
8040152	Separate configuration of I/O cells and logic core in a programmable logic device A programmable logic device (PLD) is provided that includes: a plurality of programmable logic blocks, the plurality of programmable logic blocks being associated with a first configuration data shift register operable to shift in configuration data for the pluralit...	10/18/2011
8010871	Auto recovery from volatile soft error upsets (SEUs) A method of recovering from a soft error within configuration data stored in a configured programmable logic device. The method includes repeatedly processing the configuration data stored within configuration memory of the device using an error-detection algorithm ...	08/30/2011
7992120	Congestion estimation for programmable logic devices Various techniques are provided for estimating signal congestion in a programmable logic device (PLD). In one example, a computer-implemented method of estimating signal congestion in routing resources of a PLD is provided. The routing resources comprise a plurality...	08/02/2011
7989911	Shallow trench isolation (STI) with trench liner of increased thickness In one embodiment, an integrated circuit includes a substrate having high voltage transistor regions and low voltage transistor regions. The substrate includes a first trench between and adjacent to the high voltage transistor regions, a second trench between and ad...	08/02/2011
7985656	Shallow trench isolation (STI) with trench liner of increased thickness A method of manufacturing an integrated circuit includes etching a substrate to create simultaneously a first trench between high voltage transistor regions of the substrate and a second trench between low voltage regions of the substrate. The substrate is then oxid...	07/26/2011
7969248	Oscillator tuning for phase-locked loop circuit In one example, a method of tuning an oscillator of a phase-locked loop (PLL) circuit includes adjusting a coarse control signal to select one of a plurality of frequency tuning curves of the oscillator. The method includes adjusting a fine control signal to select ...	06/28/2011
7957208	Flexible memory architectures for programmable logic devices In one embodiment, a programmable logic device includes a plurality of logic blocks; a plurality of input/output blocks; volatile configuration memory adapted to store configuration data for configuration of the logic blocks and input/output blocks; embedded block R...	06/07/2011
7944765	Programmable logic device with built in self test In one embodiment of the invention, an integrated circuit such as a programmable logic device includes volatile memory, nonvolatile memory, and a data shift register for reading data from the nonvolatile memory and for reading data from and writing data to the volat...	05/17/2011
7924054	Latency measurements for wireless communications A programmable logic device (PLD), is provided that includes: a plurality of SERDES channels; a programmable logic fabric configured to implement an interface for a standardized cellular base station system; wherein the interface receives data words from the SERDES ...	04/12/2011
7902865	Compression and decompression of configuration data using repeated data frames Various techniques are provided to compress and decompress configuration data for use with programmable logic devices (PLDs). In one example, a method includes embedding a first data frame comprising a data set from an uncompressed bitstream into a compressed bitstr...	03/08/2011
7897448	Formation of high voltage transistor with high breakdown voltage A high voltage transistor exhibiting an improved breakdown voltage and related methods are provided. For example, a method of manufacturing an integrated circuit includes etching a poly silicon layer to provide a gate stacked above a floating gate of a flash memory ...	03/01/2011
7895555	Simultaneous switching output noise estimation and reduction systems and methods Systems and methods provide improved techniques directed to simultaneous switching output (SSO) noise, which for example may be applied during the programmable logic device design process. For example in accordance with an embodiment, a method of structuring simulta...	02/22/2011
7890913	Wire mapping for programmable logic devices Various techniques for referencing components of a programmable logic device (PLD) are provided. In one example, a method of referencing wires of a routing graph of a PLD is provided. The routing graph comprises a plurality of routing graph wires and a plurality of ...	02/15/2011
7876125	Register data retention systems and methods during reprogramming of programmable logic devices Systems and methods provide register data retention techniques for a programmable logic device in accordance with one or more embodiments of the present invention. For example, in one embodiment, a programmable logic device includes a plurality of logic blocks adapt...	01/25/2011
7868654	Reading an external memory device to determine its interface characteristics for configuring a programmable logic device Various techniques are provided for determining interface characteristics of external devices. In one example, a method of configuring a programmable logic device (PLD) with configuration data stored in one or more external memory devices includes reading by the PLD...	01/11/2011
7868646	Soft error upset hardened integrated circuit systems and methods In one embodiment, a programmable logic device includes a plurality of configuration cells that store configuration data, wherein the programmable logic device is adapted to provide soft error upset (SEU) protection for the configuration cells that are reprogrammabl...	01/11/2011
7863931	Flexible delay cell architecture A flexible delay cell architecture and related methods are provided that may be used, for example, with input/output (I/O) blocks of a programmable logic device (PLD). In one implementation, a PLD includes a delay cell comprising a plurality of delay elements. The d...	01/04/2011
7844243	Receiver for differential and reference voltage signaling with programmable common mode In one embodiment of the invention, a receiver has two mux circuits, two receiver circuits, and a mixer. The muxes select first and second input signals for the receiver circuits. A p-type transistor in a transmission gate in each mux is connected (i) at its channel...	11/30/2010
7834652	Method and devices for storing a security key using programmable fuses In embodiment of the invention, a programmable logic device includes configuration memory adapted to be programmed with configuration data and a plurality of programmable fuses adapted to store a security key for use with configuration data. The security key include...	11/16/2010
7831856	Detection of timing errors in programmable logic devices In one example, a method of detecting timing errors in a configuration of a programmable logic device (PLD) includes performing a timing analysis on the PLD configuration. The PLD configuration is adapted to configure the PLD to perform a data transfer between a fir...	11/09/2010
7831754	Multiple communication channel configuration systems and methods An integrated circuit includes, in accordance with an embodiment of the present invention, a data port, a system bus for transferring information to and from the data port, and a plurality of SERDES channels. A plurality of registers associated with the plurality of...	11/09/2010
7808855	Distributed front-end FIFO for source-synchronous interfaces with non-continuous clocks In one embodiment, an integrated circuit such as an FPGA includes one or more data I/O blocks, one or more FIFOs, and a FIFO controller. At least one data I/O block receives an incoming bit stream from an external device. At least one FIFO is connected to receive a ...	10/05/2010

«First «Previous1 2 3 4 5 6 7 8 9 10 11 Next»Last»

PatentStorm

Bizarre Patents

PatentStorm News

Assignee: Lattice Semiconductor Corporation