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| Number | Title | Issue Date |
| 7804167 | Wire bond integrated circuit package for high speed I/O An integrated circuit package includes a package substrate, a die attach pad formed on the package substrate for securing a die to the package substrate, a ground bonding ring formed on the package substrate for attaching core and I/O ground bond wires between the d... | 09/28/2010 |
| 7800936 | Latch-based random access memory A latch-based integrated circuit random access memory having selectable bit write capability that is less susceptible to disturbing data stored in unselected bits during write operations by utilizing an inhibit signal to block writing of the unselected bits. ... | 09/21/2010 |
| 7760578 | Enhanced power distribution in an integrated circuit An integrated circuit structure for distributing power to one or more standard cells in an integrated circuit includes a first plurality of standard cells and a power mesh power connection structure coupled to the cells. Each of the standard cells includes first and... | 07/20/2010 |
| 7757024 | Dual porting serial advanced technology attachment disk drives for fault tolerant applications The present invention is directed to an apparatus capable of dual porting a serial advanced technology attachment (SATA) disk drive in a fault tolerant communication system, such as fiber channel. The dual porting apparatus includes two idle regenerators coupled to ... | 07/13/2010 |
| 7751609 | Determination of film thickness during chemical mechanical polishing A method and apparatus is provided for determining thickness of films or layers during chemical-mechanical planarization/polishing (CMP) of a semiconductor substrate or wafer in situ. The method may be used to determine end-point during CMP especially of oxide films... | 07/06/2010 |
| 7657774 | Low power memory controller with leaded double data rate DRAM package on a two layer printed circuit board An integrated circuit is provided that includes an execution engine and a memory controller. The execution engine is clocked at a first rate and the memory controller is clocked at a second rate that is less than the first rate. Pins on the integrated circuit can tr... | 02/02/2010 |
| 7640461 | On-chip circuit for transition delay fault test pattern generation with launch off shift A clock pulse controller includes a test clock pulse input for receiving test clock pulses. A scan enable input receives a scan enable signal having a first state and a second state. A trigger pulse input receives a trigger pulse. A clock pulse output generates a la... | 12/29/2009 |
| 7627789 | Polymorphic management of embedded devices using web interfaces In some embodiments, a method for managing embedded devices may include one or more of the following steps: (a) loading an embedded web server module, (b) loading a first webpage when loading a first embedded module, (c) replacing the first webpage with a second web... | 12/01/2009 |
| 7617391 | Method and apparatus for dynamically selecting one of multiple firmware images for booting an I/O controller A method and apparatus are disclosed in a data processing system for dynamically selecting one of multiple different I/O firmware images for booting a particular I/O controller that is included in the data processing system. Multiple different I/O firmware images ar... | 11/10/2009 |
| 7601643 | Arrangement and method for fabricating a semiconductor wafer An arrangement and method for fabricating a semiconductor wafer which utilizes a nonaqueous solvent rinse is disclosed. ... | 10/13/2009 |
| 7590819 | Compact memory management unit A memory management unit (MMU) for a device controller that provides enhanced functionality while maintaining a small physical size or footprint, such that the die size required to manufacture the memory management unit circuitry within the device controller integra... | 09/15/2009 |
| 7582566 | Method for redirecting void diffusion away from vias in an integrated circuit design A method for redirecting void diffusion away from vias in an integrated circuit design includes steps of forming an electrical conductor in a first electrically conductive layer of an integrated circuit design, forming a via between a distal end of the electrical co... | 09/01/2009 |
| 7577928 | Verification of an extracted timing model file A system, apparatus and method for generating and validating extracted timing model files, such as macro library files, are disclosed. A user interface or data template is provided to an engineer that allows for the population of data within particular fields relate... | 08/18/2009 |
| 7576977 | Shoulder screw and handle drive mounting system A computer storage enclosure may comprise a mounting chassis and a computer drive apparatus. The mounting chassis may have a plurality of computer drive guides, a plurality of cam pins, and a mounting chassis disengagement ramp. The computer drive apparatus may incl... | 08/18/2009 |
| 7574541 | FIFO sub-system with in-line correction A flow-based FIFO sub-system for a disk formatter in a data processing system that performs data width conversion. The sub-system has a first FIFO unit having a first width interfacing to a first bursting channel, and a second FIFO unit having a second width interfa... | 08/11/2009 |
| 7574353 | Transmit/receive data paths for voice-over-internet (VoIP) communication systems The present invention is a method and apparatus in a data processing system that includes a Voice over Internet Protocol (VoIP) communication system for improving transmit and receive data paths. The communication system includes a digital signal processing unit. Th... | 08/11/2009 |
| 7573870 | Transmit prioritizer context prioritization scheme A method and system prioritizes frames to be transmitted from a local node to a remote node on a Fibre Channel Arbitration Loop. The frames are placed in context queues. Each kind of context queue is assigned a priority. A determination of a set of transmit frame ty... | 08/11/2009 |
| 7571430 | Adaptive dispatch table based on templates The present invention is directed to a method of an adaptive procedure table which is capable of providing default behaviors for each procedure if a corresponding procedure is not defined or has been removed from a software build. The default behaviors for each proc... | 08/04/2009 |
| 7571397 | Method of design based process control optimization The present invention provides a method of design based process control optimization. In an embodiment, the method of design based process control optimization includes creating a circuit layout database including a design rule set. At least one algorithm is employe... | 08/04/2009 |
| 7571396 | System and method for providing swap path voltage and temperature compensation The present invention is a method for data path voltage and temperature compensation. The method includes configuring an offline data path to match an online data path. The method further includes compensating the offline data path for voltage and temperature variat... | 08/04/2009 |
| 7571370 | Configurable, fast, 32-bit CRC generator for 1-byte to 16-bytes variable width input data A method and circuit for performing CRC calculations permits variable width data input. Preferably, multiple CRC calculations are performed in parallel, each CRC calculation involving a different number of data bits from the data word and terminating within one cloc... | 08/04/2009 |
| 7568216 | Methods for defining and naming iSCSI targets using volume access and security policy The present invention is directed to methods for defining and naming iSCSI targets using volume access and security policy. In an exemplary aspect of the present invention, a method for defining an iSCSI target using volume access and security policy may include the... | 07/28/2009 |
| 7560292 | Voltage contrast monitor for integrated circuit defects A semiconductor chip is provided which includes active and inactive IP cores. The spaces on the metal layer associated with the inactive IP cores includes voltage contrast inspection structures. The voltage contrast inspection structures serve to provide improved pl... | 07/14/2009 |
| 7555688 | Method for implementing test generation for systematic scan reconfiguration in an integrated circuit A method for implementing test generation for systematic scan reconfiguration in an integrated circuit is presented. The method may comprise: defining at least one set of detectable faults; setting an SAS decoder configuration, the SAS decoder configuration includin... | 06/30/2009 |
| 7552355 | System for providing an alternative communication path in a SAS cluster The present invention is directed to a system and method for supporting an alternative peer-to-peer communication over a network in a SAS cluster when a node cannot communicate with another node through a normal I/O bus (Serial SCSI bus). At startup, driver may esta... | 06/23/2009 |
| 7548844 | Sequential tester for longest prefix search engines The present invention is directed to a sequential tester for longest prefix search engines. The tester may include a longest prefix search engine, an inputs generator for providing a nearly random flow of input commands to the longest prefix search engine and for ou... | 06/16/2009 |
| 7542508 | Continuous-time decision feedback equalizer A continuous-time domain Decision Feedback Equalizer (DFE) for use in a serial communication channel comprises in one embodiment a summer, a decision circuit, a capture flip-flop (FF) and an N-th order active filter. The DFE and its active filter operate in continuo... | 06/02/2009 |
| 7539798 | Mitigating performance degradation caused by a sata drive attached to a sas domain The present invention provides a device and method for mitigating performance degradation caused by SATA drives attached to a SAS domain. In one of the embodiments of the present invention, a SATA degradation mitigation device (“SDMD”) is installed between a SAS... | 05/26/2009 |
| 7535330 | Low mutual inductance matched inductors Multiple inductor structures and methods for providing low mutual inductance between the inductors are described. In various embodiments of the invention, the polarities of the inductors are positioned such that parasitic mutual inductance is reduced by causing elec... | 05/19/2009 |
| 7529968 | Storing RAID configuration data within a BIOS image A system, apparatus and method for storing and maintaining drive configuration data related to disk drives within a RAID. In one embodiment of the invention, configuration data is stored external to the disk drives within the RAID. A scan(s) is performed of the RAID... | 05/05/2009 |
| 7499146 | Lithographic apparatus and device manufacturing method, an integrated circuit, a flat panel display, and a method of compensating for cupping The tilt and position of individually controllable element are simultaneously adjusted to allow a greater range of contrasts to be achieved. This can also be used to compensate for cupping of individually controllable elements. Simultaneous adjustment of both the po... | 03/03/2009 |
| 7496694 | Circuit, systems and methods for monitoring storage controller status Circuits, systems and methods for improved monitoring of status of a storage controller in a storage system. A monitoring circuit external to the storage controller is adapted to couple to the internal bus structure within the storage controller. The monitoring circ... | 02/24/2009 |
| 7456498 | Integrated circuit package and system interface A method for enhancing the performance of an IC package and media interface. Adding a fissure to a Flip-Chip type package improves the crosstalk performance of the package for both high and low frequencies. The wall of the fissure can be implemented with a heat spre... | 11/25/2008 |
| 7458060 | Yield-limiting design-rules-compliant pattern library generation and layout inspection A method and system are provided for analyzing process window compliance of an integrated circuit design. Aspects of the present invention include identifying layout pattern configurations that have process windows that fail to meet respective local performance spec... | 11/25/2008 |
| 7454303 | System and method for compensating for PVT variation effects on the delay line of a clock signal The present invention is directed to a method for compensating for process, voltage, and temperature variation without complex online/offline swapping of data paths requiring a dedicated FIFO(First-in First-out) buffer design. Delay cells are trained for each clock ... | 11/18/2008 |
| 7444459 | Methods and systems for load balancing of virtual machines in clustered processors using storage related load information Methods and systems for generating storage related load factor information for load balancing of multiple virtual machines operable in a cluster of multiple physical processors (such as a blade center). Load factor information is generated within a storage system re... | 10/28/2008 |
| 7440500 | Supporting motion vectors outside picture boundaries in motion estimation process An apparatus generally having a first memory and a circuit is disclosed. The first memory may be used for a motion estimation of a current block. The circuit may be configured to (i) determine if a search window for the current block is at least partially outside a ... | 10/21/2008 |
| 7434198 | Method and computer program product for detecting potential failures in an integrated circuit design after optical proximity correction A method of detecting potential failures from a corrected mask design for an integrated circuit includes steps of receiving as input a corrected mask design for an integrated circuit, searching the corrected mask design to find a critical edge of a polygon that is c... | 10/07/2008 |
| 7430700 | Failure analysis and testing of semi-conductor devices using intelligent software on automated test equipment (ATE) The invention provides a number of related methods which improve the test and analysis of integrated circuit devices. A first method of the invention provides a method for pausing on a SCAN based test. A second method of the invention provides a method for using sti... | 09/30/2008 |
| 7409498 | Scaled coercion of disk drive capacity The present invention provides disk coercion by generating coercion percentages or values that can be used to coerce various disks according to each disk's particular labeled size or capacity. In one embodiment, a disk size is received and a base coercion scaling fa... | 08/05/2008 |
