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| Number | Title | Issue Date |
| 8179372 | Electronic display with array context-sensitive search (ACS) technology A system and method for efficient computation in the course of locating a position on the face of a touch-screen-equipped display device by limiting the amount of computations to weighted vectors within a range substantially less than the entire range of data input ... | 05/15/2012 |
| 8174428 | Compression of signals in base transceiver systems A signal compression method and apparatus for a base transceiver system (BTS) in a wireless communication network provides efficient transfer of compressed signal samples over serial data links in the system. For the uplink, an RF unit of the BTS compresses signal s... | 05/08/2012 |
| 8164367 | Spread spectrum clock generation technique for imaging applications A clock signal generator includes a phase-lock loop for generating an imaging clock signal having a frequency based on a reference clock signal. The imaging clock signal generator also includes a modulation circuit for determining a number of pixels in a horizontal ... | 04/24/2012 |
| 8160272 | Audio output circuits having ramped attenuation circuits that inhibit pop disturbances when audio sources are switched An audio output circuit includes a port attenuation circuit, which is configured to convert an abrupt dc voltage offset transition between a pair of audio signals received in sequence at an input thereof into a more gradual transition. This conversion is achieved by... | 04/17/2012 |
| 8154880 | Method and apparatus for active line interface isolation A method and apparatus for active line interface isolation have been described. ... | 04/10/2012 |
| 8151132 | Memory register having an integrated delay-locked loop A memory device is provided. The memory device includes a plurality of memory chips coupled in series, and a register serially coupled to the memory chips. The register includes an integrated delay-locked loop. The memory device may be included in a processing syste... | 04/03/2012 |
| 8149224 | Computing system with detachable touch screen device A computing system includes a computer device and a detachable touch screen device. The computer device receives input from a touch screen of a detachable touch screen device when the detachable touch screen device is attached to a touch screen port of the computer ... | 04/03/2012 |
| 8138845 | Method and apparatus for auto-frequency calibration for multi-band VCO A method and apparatus for auto-frequency calibration for multi-band VCO have been disclosed where a VCO is first adjusted to a major frequency band and then adjusted to a sub-band within the major frequency band. ... | 03/20/2012 |
| 8134414 | Clock, frequency reference, and other reference signal generator with frequency stability over temperature variation Exemplary embodiments provide a reference signal generator having a reference or center frequency within a predetermined variance over variations in temperature within a specified range. An exemplary apparatus comprises a reference resonator to generate a first refe... | 03/13/2012 |
| 8127187 | Method and apparatus of ATE IC scan test using FPGA-based system An apparatus and a method for enhancing the use of automated test equipment (ATE), are presented. The apparatus comprises a test load board that mounts a plurality of devices to be tested (DUTs), and a daughter card communicating with the test board and the ATE, tes... | 02/28/2012 |
| 8120405 | Method and apparatus for an output buffer with dynamic impedance control A method and apparatus for an output buffer with dynamic impedance control have been disclosed. ... | 02/21/2012 |
| 8120162 | Package with improved connection of a decoupling capacitor A package (216) for electrically connecting an integrated circuit (212) to a printed circuit board (214) includes a mount array (219) and a substrate body (216A). The mount array (219) is electrically connected to the integr... | 02/21/2012 |
| 8115532 | Linear monotonic delay chain circuit A method and circuit for generating an adjustable delay signal is presented, wherein the delay can be linear and monotonic with high resolution delay steps. The circuit utilizes one or more serially coupled delay cells and a load cell. Each delay cell comprises an i... | 02/14/2012 |
| 8095707 | Method for synchronization of peripherals with a central processing unit in an embedded system A method and apparatus for synchronizing I/O peripherals with a CPU in an embedded system is discussed. The method involves receiving an address from the CPU in response to a read and/or write access, translating the address received from the CPU to identify a I/O p... | 01/10/2012 |
| 8094677 | Multi-bus structure for optimizing system performance of a serial buffer A serial buffer having a parser and multiple parallel processing paths is provided. The parser receives incoming packets, determines the type of each packet, and then routes each packet to a processing path that corresponds with the determined packet type. Packet ty... | 01/10/2012 |
| 8093958 | Clock, frequency reference, and other reference signal generator with a controlled quality factor Exemplary embodiments of the invention provide a reference signal generator having a controlled quality (“Q”) factor. An exemplary apparatus to generate a harmonic reference signal includes a reference resonator, such as an LC-tank, which generates a first refer... | 01/10/2012 |
| 8093957 | Method and apparatus for frequency compensation for multi-band VCO A method and apparatus for frequency compensation for multi-band VCO have been disclosed where a VCO tank loading capacitance is adjusted slowly to allow VCO operation in a linear range. ... | 01/10/2012 |
| 8085603 | Method and apparatus for compression of configuration bitstream of field programmable logic A memory is disclosed that can be utilized with a field programmable gate array. In some embodiments, the memory can include a memory array comprising a plurality of memory banks, each memory bank including at least one memory block, each of the at least one memory ... | 12/27/2011 |
| 8085180 | Apparatuses and methods for multiple-output comparators and analog-to-digital converters An analog-to-digital converter with comparators with multiple, inter-coupled, outputs is provided, which may be also called a Benorion Analog-to-Digital Converter (ADC) or a Benorion Converter. The analog-to-digital converter includes a plurality of comparators oper... | 12/27/2011 |
| 8081646 | Old virtual queues technique for routing data packets in a packet switch A packet switch includes virtual output queues for mapping data units of data packets from input ports to output ports of the packet switch. The packet switch selects virtual output queues based on old age indicators of the virtual output queues and routes data unit... | 12/20/2011 |
| 8081031 | Equalization system with stabilized peaking gain for a communication system An equalization system (18) that reduces inter-symbol interference in an input signal (220) includes a variable gain amplifier (430), and one or more peaking amplifiers (432) that are connected in series to the variable gain amplifier ( | 12/20/2011 |
| 8073090 | Synchronous de-skew with programmable latency for multi-lane high speed serial interface A method and system for performing clock calibration and de-skew on a multi-lane high speed serial interface is presented. Each of a plurality of serial lane transceivers associated with an individual bit lane receives a first data frame, comprising a training seque... | 12/06/2011 |
| 8073043 | Method for reliable injection of deterministic jitter for high speed transceiver simulation A method and a corresponding system for characterizing the performance of a clock and data recovery circuit in a digital transceiver is presented. The method comprises phase modulating a jitter-free data signal by a testing signal having added data jitter and measur... | 12/06/2011 |
| 8072259 | Voltage reference and supply voltage level detector circuits using proportional to absolute temperature cells N-channel field effect transistor Proportional To Absolute Temperature (N-PTAT) cells are connected to a first supply voltage and P-channel field effect transistor Proportional To Absolute Temperature (P-PTAT) cells are connected to a second supply voltage. A coupli... | 12/06/2011 |
| 8069392 | Error correction code system and method An error correction code system includes an error correction code generator for generating an error correction code based on a data unit and an error detector for detecting at least one bit error in the data unit based on the error correction code. The error correct... | 11/29/2011 |
| 8064472 | Method and apparatus for queue concatenation A method and apparatus for queue concatenation have been disclosed. ... | 11/22/2011 |
| 8063683 | Low power clock and data recovery phase interpolator A phase interpolator is provided. The phase interpolator comprises a plurality of reference stages, the reference stages receiving a reference signal having a predetermined phase and outputting a component signal, wherein the reference stages comprise a plurality of... | 11/22/2011 |
| 8040888 | Packet switch with port route tables A packet switch includes individual route tables for ports of the packet switch. Each route table is associated with a port and individually maps a destination identifier of a data packet received at the port to another port in the packet switch. In some embodiments... | 10/18/2011 |
| 8036216 | Method and apparatus for packet cut-through A method and apparatus for packet cut-though have been disclosed. In packet cut-through mode successive packet fragments are associated an identical logical data flow. This allows, for example, a SPI-4 interface to be able to successively transmit a whole packet for... | 10/11/2011 |
| 8031099 | Analog/digital or digital/analog conversion system having improved linearity A digital-to-analog converter (DAC) circuit includes a least significant bit (LSB) set of capacitors, each commonly coupled to an LSB node, and a most significant bit (MSB) set of capacitors, each coupled to an MSB node. A section-coupling capacitor couples the LSB ... | 10/04/2011 |
| 8028211 | Look-ahead built-in self tests with temperature elevation of functional elements A method and apparatus are disclosed for predicting the failure of a functional element of an integrated circuit during operation. The method includes determining whether the functional element of the integrated circuit device is in an idle cycle, elevating the temp... | 09/27/2011 |
| 8023594 | Asynchronous biphase mark signal receivers and methods of operating same A biphase mark signal receiver includes a data and clock recovery circuit. The data recovery circuit may include a coarse recovery stage and a fine recovery stage. The coarse recovery stage is configured to detect repeating occurrences of a first preamble (e.g., Y-p... | 09/20/2011 |
| 8022738 | Apparatus and method for detecting the loss of an input clock signal for a phase-locked loop An apparatus is provided for detecting the loss of an input clock signal for a phase-locked loop (PLL). The apparatus includes a time delay circuit, a first frequency divider and a digital logic circuit. The time delay circuit receives the input clock signal and out... | 09/20/2011 |
| 8018289 | Holdover circuit for phase-lock loop A clock circuit includes a phase-lock loop and a holdover circuit. The phase-lock loop generates an output clock signal having a constant frequency based on a loop filter voltage of a loop filter in the phase-lock loop. The holdover circuit generates and stores a di... | 09/13/2011 |
| 8014288 | Packet latency based arbitration technique for a packet switch A packet switch including input ports having various input bandwidths initializes credit values for the input ports. An arbiter of the packet switch selects input ports based on the credit values and routes data packets from the selected input ports to a switch fabr... | 09/06/2011 |
| 8009719 | Digital spread spectrum method based on precise phase delta-sigma algorithm A method and apparatus for generating a spread spectrum reference clock is presented. A method and apparatus is presented for receiving a spread spectrum parameter from a phase lock loop, wherein the spread spectrum parameter includes a multiple-level parameter comp... | 08/30/2011 |
| 8008951 | High voltage switch utilizing low voltage MOS transistors with high voltage breakdown isolation junctions A high voltage switch having first and second states includes an input receiving an input voltage that is greater than a supply voltage. Each of first, second, and third MOS structures of a first conductivity type has a gate, a source, and a drain. The sources and d... | 08/30/2011 |
| 8008927 | Method and apparatus for ground bounce and power supply bounce detection A method and apparatus for ground bounce and power supply bounce detection in devices have been disclosed. In one case one input to a differential amplifier is coupled to a reference voltage and another input to the differential amplifier is coupled to a measurement... | 08/30/2011 |
| 8004339 | Apparatuses and methods for a level shifter with reduced shoot-through current A level-shifting circuit with reduced shoot-through current includes an output circuit comprising high-voltage devices with a pull-up circuit configured for pulling up a voltage on an output signal to a high voltage responsive to a high-side control signal. The outp... | 08/23/2011 |
| 7995698 | Method for binary clock and data recovery for fast acquisition and small tracking error A novel method and system for clock and data recovery in high speed serial transceiver applications allowing for fast bit lock acquisition and small data tracking error is presented. The clock and data recovery method utilizes a variable bandwidth loop filter to gen... | 08/09/2011 |
