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| Number | Title | Issue Date |
| 7427774 | Targets for measurements in semiconductor devices Targets or test structures used for measurements in semiconductor devices having long lines exceeding design rule limitations are divided into segments. In one embodiment, the segments have periodicity in a direction parallel to the length of the lines. In another e... | 09/23/2008 |
| 7402487 | Process for fabricating a semiconductor device having deep trench structures A process for fabricating a semiconductor device having deep trench structures includes forming a first portion of the trench in a semiconductor substrate and a second portion of the trench in a selectively-formed upper layer. After etching the substrate to form the... | 07/22/2008 |
| 7381576 | Method and apparatus for monitoring precision of water placement alignment A method for monitoring precision of placement of semiconductor wafers in a semiconductor processing apparatus includes measuring thickness of an insulating film on a surface of a semiconductor substrate before etching a portion of the insulating film from the surfa... | 06/03/2008 |
| 7358493 | Method and apparatus for automated beam optimization in a scanning electron microscope A method and apparatus according to the present invention define optimal conditions for a scanning electron microscope (SEM), preferably a critical dimension scanning electron microscope (CDSEM). The present invention provides an image quality monitor that utilizes ... | 04/15/2008 |
| 7351642 | Deglaze route to compensate for film non-uniformities after STI oxide processing A process and method for compensating for a radial non-uniformity on a wafer that includes the steps of: centering a rotational thickness non-uniformity of a film on the wafer about the axis of the spin susceptor following a CMP process; positioning a nozzle in the ... | 04/01/2008 |
| 7279258 | Method and arrangement for controlling focus parameters of an exposure tool A pattern can be projected on a resist film layer deposited on a semiconductor surface. The pattern can include structural elements having different feature sizes. Structural elements having feature sizes below a certain limit are not resolved on the resist film lay... | 10/09/2007 |
| 7214552 | Eliminating systematic process yield loss via precision wafer placement alignment A method for a semiconductor process includes correlating yield loss for the performance of a processing step in a semiconductor manufacturing process with the mechanical placement of the semiconductor substrate and, based on the correlation, placing semiconductor s... | 05/08/2007 |
| 7184853 | Lithography method and system with correction of overlay offset errors caused by wafer processing A method of controlling lithographic overlay offsets in the manufacture of semiconductor devices from wafers, comprising the steps of forming a lithographic pattern on a wafer layer with a lithographic tool, processing the wafer after the pattern is formed to enable... | 02/27/2007 |
| 7051253 | Pseudo fail bit map generation for RAMS during component test and burn-in in a manufacturing environment According to an embodiment of the present invention, a method is provided for determining a fail string for a device. The method includes determining a test pattern for a portion of an address space wherein the test pattern includes at least one address in the addre... | 05/23/2006 |
| 7003432 | Method of and system for analyzing cells of a memory device A method of analyzing cells of a memory device is disclosed. Generally, a plurality of fail signatures is generated, wherein each fail signature is associated with a type of failure. Voltages according to a plurality of test patterns are applied to nodes of a cell o... | 02/21/2006 |
| 6927462 | Method of forming a gate contact in a semiconductor device A processing sequence for definition of gate contacts can be implemented using either a deep ultra-violet (DUV) or mid ultra-violet (MUV) positive resist processing and supports the use of a reticle that integrates contacts to various regions including gates, source... | 08/09/2005 |
| 6828249 | System and method for enhanced monitoring of an etch process A method for monitoring an etch process of a substrate that includes receiving a first signal having a first wavelength, deriving a second signal based on the first signal and combining the first signal with the second signal to produce a composite signal having a c... | 12/07/2004 |
| 6725403 | Efficient redundancy calculation system and method for various types of memory devices A method for calculating and analyzing redundancies for semiconductor memories, in accordance with the present invention, includes providing a memory device including at least one memory chip. The at least one memory chip includes a redundancy calculation region. Th... | 04/20/2004 |
| 6696349 | STI leakage reduction A semiconductor device is provided having at least two neighboring transistors and an STI region therebetween. The STI region is provided with a voltage bias to minimize subthreshold leakage current between the neighboring transistors. A method of fabrica... | 02/24/2004 |
| 6564346 | Advanced bit fail map compression with fail signature analysis A method for providing a compressed bit fail map, in accordance with the invention includes the steps of testing a semiconductor device to determine failed devices and transferring failure information to display a compressed bit map by designating areas o... | 05/13/2003 |
