Assignee: Infineon Technologies Flash GmbH & Co. KG

Location: Dresden, DE
No. of patents: 36

Number	Title	Issue Date
7660142	Device with memory and method of operating device A method of operating an electronic device includes storing a first plurality of bits of digital information in a memory using a first number of memory cells in parallel. The first plurality of bits of digital information are for operating the device when operating ...	02/09/2010
7564718	Method for programming a block of memory cells, non-volatile memory device and memory card device A method is provided for programming a block of memory cells of a non-volatile memory device. A first group of memory cells of the block of memory cells is selected. At least one programming pulse is programmed into all memory cells of the first group. A threshold l...	07/21/2009
7548477	Method and apparatus for adapting circuit components of a memory module to changing operating conditions A method adapts circuit components of a memory module to changing operating conditions within a predefined range. According to one embodiment, a memory module provides a sensor arrangement and a communication bus. Sub-ranges are defined for at least one operating co...	06/16/2009
7522461	Memory device architecture and method for improved bitline pre-charge and wordline timing A memory device architecture having improved bitline pre-charge and wordline timing operations includes a pre-charge driver, a pre-charge line, a timing controller, a wordline driver, and a wordline coupled to a selected memory cell. The pre-charge driver is operabl...	04/21/2009
7502916	Processing arrangement, memory card device and method for operating and manufacturing a processing arrangement A processing arrangement (1) includes a processing unit (3) adapted to execute a predetermined set of processing instructions received from an instruction input (12). The set of processing instructions includes at least one predetermined process...	03/10/2009
7434121	Integrated memory device and method for its testing and manufacture An integrated memory device includes an array of memory cells for storing data, a memory cell selector operationally connected to the array for selecting at least one memory cell of the array, a data interface adapted to store data provided to the data interface in ...	10/07/2008
7427548	Method for producing charge-trapping memory cell arrays A memory layer sequence comprising a lower confinement layer (2), a charge-trapping layer (3), and an upper confinement layer (4) is applied on the main surface of a silicon substrate (1). By a photolithography step, trenches running para...	09/23/2008
7411844	Semiconductor memory device having a redundancy information memory directly connected to a redundancy control circuit A semiconductor memory device (M) includes a memory array (MA) having a plurality of memory cells, a redundancy array (RA) having a plurality of memory cells, a non-volatile redundancy information memory (NVR) having a plurality of memory cells for storing redundanc...	08/12/2008
7410102	Non-volatile memory card with autarkic chronometer A non-volatile memory card is described, which comprises a chronometer powered by an autarkic, card-internal power supply with a long-term energy store. The chronometer is connected to a card internal controller, such that the chronometer can provide the current tim...	08/12/2008
7409609	Integrated circuit with a control input that can be disabled An integrated circuit comprises a control unit, a plurality of control inputs for the provision of control signals to said control unit and a deactivation circuit for disabling the provision of at least one of said control signals. After reception of a first coded m...	08/05/2008
7403438	Memory array architecture and method for high-speed distribution measurements A method includes an initial process of selecting a memory cell within the memory array and an operating condition under which the memory cell is to be tested. The memory cell is tested under the specified operating condition, and a measured response obtained theref...	07/22/2008
7403417	Non-volatile semiconductor memory device and method for operating a non-volatile memory device Embodiments of the invention relate to non-volatile memory devices and their methods of manufacture. Embodiments comprise an array of non-volatile memory cells, the array comprising a multiplicity of array columns having at least one redundant column of non-volatile...	07/22/2008
7355909	Column redundancy reuse in memory devices A method for column redundancy re-use includes arranging the memory array into a plurality of addressable first array columns and a plurality of addressable second array columns. The column redundancy structure is also arranged into an addressable first redundancy c...	04/08/2008
7355468	Voltage generator circuit, method for providing an output voltage and electronic memory device A voltage generator circuit provides an output voltage that is higher than an input voltage. The voltage generator circuit includes an input terminal receiving the input voltage, and an output terminal providing the output voltage. A pre-charge element is coupled be...	04/08/2008
7348660	Semiconductor package based on lead-on-chip architecture, the fabrication thereof and a leadframe for implementing in a semiconductor package A leadframe includes a multiplicity of leads. The leads have a board level contact portion, an intermediate portion and a chip level contact portion. The intermediate portion is disposed between the board level contact portion and the chip level contact portion. The...	03/25/2008
7342829	Memory device and method for operating a memory device A memory device (1) includes a memory array (2). The memory array (2) has at least one memory area (5) that includes a plurality of conductive lines (3) and a plurality of memory cells (4) connected to the conductive lines (...	03/11/2008
7341904	Capacitorless 1-transistor DRAM cell and fabrication method A semiconductor device is fabricated by forming a trench in a semiconductor body. A region of dielectric material is formed within at least a lower portion of the trench. An upper portion of the semiconductor body is doped. A cutout is formed in the semiconductor ma...	03/11/2008
7323388	SONOS memory cells and arrays and method of forming the same A trench (2) is fabricated in a silicon body (1). The walls (4) of the trench are provided with a nitrogen implantation (6). An oxide layer between the source/drain regions (5) and a word line applied on the top side grows to a gre...	01/29/2008
7295477	Semiconductor memory device and method for writing data into the semiconductor memory device A semiconductor memory device comprises a wordline (40), a first bitline (21a), two second bitlines (22a, 22b), a first memory cell (100a) and a second memory cell (100b). The first memory ...	11/13/2007
7283395	Memory device and method for operating the memory device A memory device comprises a memory cell array (1) with a multitude of memory cells (111). Each of the memory cells (111) is assigned to one of a multitude of blocks (15). Each memory cell (111) is accessible by an access signal in ...	10/16/2007
7274597	Method of programming of a non-volatile memory cell comprising steps of applying constant voltage and then constant current A method and arrangement are provided for programming an electrically erasable programmable read-only memory cell capable of storing at least one information bit. The memory cell has a charge-trapping region. According to the invention, during a first period of time...	09/25/2007
7259993	Reference scheme for a non-volatile semiconductor memory device A non-volatile semiconductor memory device is provided comprising a memory area and a circuitry area. The memory area includes a plurality of memory cells and a set of array reference cells that are programmable to have a threshold voltage corresponding to an erased...	08/21/2007
7242623	Non-volatile memory cell device, programming element and method for programming data into a plurality of non-volatile memory cells A programming element for programming data into a plurality of non-volatile memory cells of a non-volatile memory cell array, the data being transferred to the non-volatile memory cell array in a data word comprising a plurality of data items. The programming elemen...	07/10/2007
7233514	Non-volatile semiconductor memory and method for reading a memory cell A method for reading a memory cell, wherein the memory cell comprises two source/drain regions and a gate, wherein the source/drain regions are each connected to a respective local bitline, and, wherein one of the source/drain regions of a neighboring memory cell is...	06/19/2007
7205195	Method for fabricating NROM memory cells with trench transistors An electrically conductive bit line layer is applied and patterned into portions arranged parallel to one another before the trench is etched into the semiconductor material, in which case, after the patterning of the bit line layer (3, 4) and before the etch...	04/17/2007
7203096	Method and apparatus for sensing a state of a memory cell A cell arrangement comprising a memory cell arranged in parallel to a first capacitor is charged to a first voltage potential. A second capacitor is charged to a second voltage potential, which is higher than the first voltage potential. The second capacitor is conn...	04/10/2007
7190621	Sensing scheme for a non-volatile semiconductor memory cell A method of sensing a state of a non-volatile semiconductor memory cell is provided. A memory cell current as well as a comparative current generated from at least one reference cell are compared with a predefined reference current while the gate voltages of the cel...	03/13/2007
7190605	Semiconductor memory and method for operating a semiconductor memory comprising a plurality of memory cells A method for operating a semiconductor memory (M) including a plurality of memory cells (MC), wherein the memory cells (MC) are arranged adjacent to one another, the arrangement starts with a first memory cell (MF) and ends with a last memory cell (ML), each memory ...	03/13/2007
7187589	Non-volatile semiconductor memory and method for writing data into a non-volatile semiconductor memory Data is written into a non-volatile semiconductor memory using one of at least four steps. A first step is executed if the final states of both the first bit (B1) and the second bit (B2) coincide with their respective initial states and includes mainta...	03/06/2007
7184291	Semiconductor memory having charge trapping memory cells and fabrication method In the case of this semiconductor memory having NROM cells, the channel regions of the memory transistors in each case run transversely with respect to the relevant word line, the bit lines are arranged on the top side of the word lines and in a manner electrically ...	02/27/2007
7158416	Method for operating a flash memory device An error correction code is applied and an erasing procedure is passed as accomplished, if a maximum number of single bit failures in compliance with a criterion of the error correction code is not exceeded. ...	01/02/2007
7121473	Security memory card and production method A microcontroller and a memory having a large storage capacity are arranged in a module having a thickness of a smart card and lateral dimensions reduced in comparison therewith, and also has first connection pads (as used for smart cards) and second connection pads...	10/17/2006
7094648	Method for fabricating an NROM memory cell array In the method, trenches are etched and, in between, bit lines (8) are in each case arranged on doped source/drain regions (3, 4). Storage layers (5, 6, 7) are applied and gate electrodes (2) are arranged at the trench walls. After the int...	08/22/2006
7075137	Semiconductor memory having charge trapping memory cells In a charge trapping memory architecture for virtual ground with interconnects (6) that are present parallel to the word lines (2) and STI isolations (1) that are present parallel to the bit lines (4), provision is made of STI isolations ...	07/11/2006
7034336	Capacitorless 1-transistor DRAM cell and fabrication method The channel region (11) and the source-drain regions (9, 10) are arranged vertically at a sidewall of a dielectric trench filling (4). On the opposite side, the semiconductor material is bounded by the gate dielectric (18) and the gate el...	04/25/2006
6913987	Method for fabricating self-aligned contact connections on buried bit lines Word lines of a semiconductor component are provided with an encapsulation of dielectric material, Spacers of oxide extend alongside at the sidewalls of the word lines. The spacers are subsequently covered together with the word lines with a nitride layer. Borophosp...	07/05/2005

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Assignee: Infineon Technologies Flash GmbH & Co. KG