Bizarre Patents
Crispy Chip Sandwich and Process of Producing a Sandwich Product
A food product comprising a multilayer cookie or snack having outer layers formed from a crispy type edible food product such as a potato chip or corn chip, etc. with an intermediate marshmallow layer being in contact with the inner surface of each crispy chip and one or more filler substances.
PatentStorm News
Make the Most of Our Site
See this month's Top Inventors and Most Cited Patents.
Stay on top of the latest innovations by subscribing to an RSS feed.
Registered users: Manage your profile.
| Number | Title | Issue Date |
| 8185369 | Method and apparatus for characterizing properties of electronic devices depending on device parameters A system and method for obtaining information about an electronic device includes the steps of providing a criterion for a property of the electronic device depending on at least one device parameter, and determining a relationship between variations of the at least... | 05/22/2012 |
| 8183129 | Alignment marks for polarized light lithography and method for use thereof Mark and method for integrated circuit fabrication with polarized light lithography. A preferred embodiment comprises a first plurality of elements comprised of a first component type, wherein the first component type has a first polarization, and a second plurality... | 05/22/2012 |
| 8178965 | Semiconductor module having deflecting conductive layer over a spacer structure A module includes a semiconductor chip and a conductive layer arranged over the semiconductor chip. The module also includes a spacer structure arranged to deflect the conductive layer away from the semiconductor chip. ... | 05/15/2012 |
| 8178902 | CMOS transistor with dual high-k gate dielectric and method of manufacture thereof A CMOS device with transistors having different gate dielectric materials and a method of manufacture thereof. A CMOS device is formed on a workpiece having a first region and a second region. A first gate dielectric material is deposited over the second region. A f... | 05/15/2012 |
| 8173502 | Formation of active area using semiconductor growth process without STI integration A semiconductor device can be formed without use of an STI process. An insulating layer is formed over a semiconductor body. Portions of the insulating layer are removed to expose the semiconductor body, e.g., to expose bare silicon. A semiconductor material, e.g., ... | 05/08/2012 |
| 8169069 | Integrated semiconductor outline package A transistor outline package is provided for a semiconductor integrated device suitable for use in a control module of an automobile for connection between a printed circuit board and a bus bar of such a module. The package includes a package housing, having a first... | 05/01/2012 |
| 8169033 | Semiconductor devices and methods of manufacture thereof Methods of forming transistors and structures thereof are disclosed. A preferred embodiment comprises a semiconductor device including a workpiece, a gate dielectric disposed over the workpiece, and a thin layer of conductive material disposed over the gate dielectr... | 05/01/2012 |
| 8158478 | Strained semiconductor device and method of making same In a method of making a semiconductor device, a gate dielectric is formed over the semiconductor body. A floating gate is formed over the gate dielectric, an insulating region over the floating gate, and a control gate over the insulating region. The gate dielectric... | 04/17/2012 |
| 8148821 | Dense seed layer and method of formation Methods of forming dense seed layers and structures thereof are provided. Seed layers including a monolayer of molecules having a density of about 0.5 or greater may be manufactured over a metal layer, resulting in a well-defined interface region between the metal l... | 04/03/2012 |
| 8148235 | Methods of manufacturing semiconductor devices Methods of forming air gaps between interconnects of integrated circuits and structures thereof are disclosed. A first insulating material is deposited over a workpiece, and a second insulating material having a sacrificial portion is deposited over the first insula... | 04/03/2012 |
| 8147615 | Method of fabricating semiconductor cleaners A method of manufacturing cleaning solvents is provided. The method includes selecting a small plurality of test solvents from a large plurality of perspective solvents. The equilibrium composition of a multi-component solution is preferably described by the Hansen ... | 04/03/2012 |
| 8138055 | Semiconductor devices having pFET with SiGe gate electrode and embedded SiGe source/drain regions and methods of making the same In a method of making a semiconductor device, a first gate stack is formed on a substrate at a pFET region, which includes a first gate electrode material. The source/drain regions of the substrate are etched at the pFET region and the first gate electrode material ... | 03/20/2012 |
| 8134388 | Low EMC/EMI emissions' gate driver for wide supply voltage ranges A method controls a power MOS transistor having a control terminal and a load path, the load path connected in series with a load between voltage supply terminals, wherein a power supply voltage between the voltage supply terminals imposes a load voltage across the ... | 03/13/2012 |
| 8124483 | Semiconductor devices and methods of manufacture thereof Semiconductor devices and methods of manufacture thereof are disclosed. In a preferred embodiment, a method of manufacturing a semiconductor device includes forming a transistor, the transistor including a fin having a first side and a second side opposite the first... | 02/28/2012 |
| 8120161 | Semiconductor module including semiconductor chips coupled to external contact elements A component includes a first semiconductor chip attached to a first carrier and second semiconductor chip attached to a second carrier. The first carrier has a first extension, which forms a first external contact element. The second carrier has a second extension, ... | 02/21/2012 |
| 8116142 | Method and circuit for erasing a non-volatile memory cell The present invention is a method, circuit and system for erasing a non-volatile memory cell. A shunting element (e.g. transistor) may be introduced and/or activated between bit-lines to which one or more NVM cells being erased are connected. The shunting element ma... | 02/14/2012 |
| 8115294 | Multichip module with improved system carrier A power semiconductor device has a first chip carrier part (11) and a second chip carrier part (12), the first chip carrier part (11) and the second chip carrier part (12) being spaced apart from one another and being electrically conduct... | 02/14/2012 |
| 8115279 | Semiconductor devices and methods of manufacture thereof Semiconductor devices and methods of manufacture thereof are disclosed. In a preferred embodiment, a semiconductor device includes a workpiece having a buried layer disposed beneath a top portion of the workpiece. An isolation ring structure is disposed within the t... | 02/14/2012 |
| 8108862 | Out-of-order thread scheduling based on processor idle time thresholds The invention relates to a device to be used with a thread scheduling method, and to a thread scheduling method comprising the steps of performing a scheduling for threads to be executed by a multithreaded (MT) processor (11), characterized in that the schedu... | 01/31/2012 |
| 8104667 | Method for connecting a component with a substrate An apparatus for connecting a component with a substrate by means of diffusion soldering in a closed evacuated chamber, wherein the component and the substrate to be connected are displaceable separate from one another in the chamber, and the chamber comprises a com... | 01/31/2012 |
| 8102041 | Integrated circuit package Two integrated circuits having circuitry on one of their major surfaces are ground on their opposite major surfaces to reduce their thickness. The ground integrated circuits are then adhered together to form a composite body and placed in a chamber formed within a s... | 01/24/2012 |
| 8101985 | Capacitors and methods of manufacture thereof Capacitors are formed in metallization layers of semiconductor device in regions where functional conductive features are not formed, more efficiently using real estate of integrated circuits. The capacitors may be stacked and connected in parallel to provide increa... | 01/24/2012 |
| 8097936 | Component, power component, apparatus, method of manufacturing a component, and method of manufacturing a power semiconductor component A component has a device applied to a device carrier, a first conducting layer grown onto the device and onto the device carrier, and an insulating material applied to the first conducting layer such that only a portion of the first conducting layer is covered. ... | 01/17/2012 |
| 8093150 | Methods of manufacturing semiconductor devices and structures thereof Methods of manufacturing semiconductor devices are disclosed. A preferred embodiment comprises a method of manufacturing a semiconductor device, the method including providing a workpiece, disposing an etch stop layer over the workpiece, and disposing a material lay... | 01/10/2012 |
| 8092958 | Mask and method for patterning a semiconductor wafer A mask and method for patterning a semiconductor wafer is disclosed. A mask set is fabricated on a transparent substrate. A mask layer comprising mask region elements that transmit light is disposed on the substrate, wherein each mask element is segmented into a plu... | 01/10/2012 |
| 8091217 | Contact element, contact unit, method for producing a contact unit, and method for placing into operation for fine-pitch parts A contact element for producing an electric contact has a laser cut conducting plate, with the contour of the laser cut conducting plate including at least two tips, which are embodied as contact tips for a contact pad of a part, connected to each other by a separat... | 01/10/2012 |
| 8089768 | Component arragement with an optimized assembly capability The invention relates to a component arrangement. In at least one embodiment, the component arrangement comprises: an electronics module; a heat sink contacted by the electronics module; a printed circuit board, and; a fastening means for fastening the electronics m... | 01/03/2012 |
| 8085887 | Method and receiver circuit for reducing RFI interference In a method for generating a compensation signal for the compensation of at least one RFI interference signal that, in a DMT transmission, is permanently superposed on a received DMT reception signal being divided into a multiplicity of channels at least one referen... | 12/27/2011 |
| 8085006 | Shunt regulator A shunt regulator for stepping down an input potential to an output potential, has an input for applying the input potential, an output for tapping off the output potential and a voltage drop circuit, across which the voltage difference between the input potential a... | 12/27/2011 |
| 8084861 | Connection structure semiconductor chip and electronic component including the connection structure and methods for producing the connection structure Connection structure (5) for attaching a semiconductor chip (2) to a metal substrate (4) is provided which has a plurality of electrically conducting layers (11, 12, 13, 14) arranged in a stack. The stack has a contact layer (11) f... | 12/27/2011 |
| 8076228 | Low noise transistor and method of making same A low noise transistor and a method of making a low noise transistor. A noise-reducing agent is introduced into the gate electrode and then moved into the gate dielectric of a transistor. ... | 12/13/2011 |
| 8076055 | Passivation of multi-layer mirror for extreme ultraviolet lithography A reflector structure suitable for extreme ultraviolet lithography (EUVL) is provided. The structure comprises a substrate having a multi-layer reflector. A capping layer is formed over the multi-layer reflector to prevent oxidation. In an embodiment, the capping la... | 12/13/2011 |
| 8067135 | Metrology systems and methods for lithography processes Metrology systems and methods for lithography processes are disclosed. In one embodiment, a method of manufacturing a semiconductor device includes providing a mask having a plurality of corner rounding test patterns formed thereon. A first semiconductor device is p... | 11/29/2011 |
| 8064862 | Antenna diversity method with fallback and weighting In a radio communication station having N antennas an antenna diversity system and a gain controllable amplifier the gain of the gain controllable amplifier is set by using a first antenna, the signal levels of signals received at the antennas is measured, a group o... | 11/22/2011 |
| 8064557 | Programmable synchronization unit for a signal receiver A programmable synchronizing unit for a signal receiver has a received data memory for buffering received data, a correlation value data memory for storing correlation values, a data path for correlating the received data with the correlation values, a result data m... | 11/22/2011 |
| 8063406 | Semiconductor device having a polysilicon layer with a non-constant doping profile Various illustrative embodiments of methods for manufacturing a semiconductor device are described. These methods may include, for example, forming a first polysilicon layer above a substrate, wherein the first polysilicon layer comprises a doped portion, and formin... | 11/22/2011 |
| 8059375 | Circuit arrangement and method for the protection of a circuit against electrostatic discharges Illustrative apparatuses and methods for electrostatic discharge protection are described in which the frequency of a voltage received at a first circuit node is filtered to generate a filtered voltage, one or more control signals are generated having either a first... | 11/15/2011 |
| 8053890 | Microchip assembly including an inductor and fabrication method An assembly includes a substrate, a chip mounted on the substrate, a voltage controlled oscillator circuit including an inductor and further circuit elements. The inductor is mounted on or in the substrate, and the further circuit elements are mounted on or in the c... | 11/08/2011 |
| 8043934 | Methods of use and formation of a lateral bipolar transistor with counter-doped implant regions under collector and/or emitter regions A method for protecting a semiconductor circuit from electrostatic discharge is disclosed. An electrostatic discharge is received at a node. Current created by the electrostatic discharge is directed vertically into a semiconductor body, laterally through the semico... | 10/25/2011 |
| 8031532 | Methods of operating embedded flash memory devices Flash memory device structures and methods of manufacture thereof are disclosed. The flash memory devices are manufactured on silicon-on-insulator (SOI) substrates. Shallow trench isolation (STI) regions and the buried oxide layer of the SOI substrate are used to is... | 10/04/2011 |
