Did You Know...
...that several people are credited with the invention of the flush toilet? Most people have heard of Thomas Crapper (1837-1910), the sanitary engineer who invented the valve-and-siphon arrangement that made the modern toilet possible. Another claimant to "the throne" was British inventor Alexander Cumming who patented a toilet in 1775. Then there's a nameless Minoan (a native of ancient Crete) who lived 4,000 years ago who supposedly was ahead of his time and created the first flush toilet!
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| Number | Title | Issue Date |
| 8156185 | Method and system for monitoring the status of an online transaction The invention includes methods and software for presenting a user with a set of interfaces that reveal what events are to occur, or are likely to occur, in a transaction, and provide the ability to program the automatic monitoring of these anticipated events with a ... | 04/10/2012 |
| 7490141 | Ajax proxy indirection for external domain requests An Ajax proxy indirection technique enables a local, front-end proxy server to handle Ajax requests from an Ajax client that must be serviced by an external Ajax server in an external domain, instead of a local Ajax back-end server exposing itself to the external do... | 02/10/2009 |
| 7231501 | Method for avoiding aliased tokens during abnormal communications A data initiator device designates an initial data tag set for tagging data transfers to thereby attach data tags from the designated set to commands directed to data transfers between the data initiator device and a data target device subsequent to the designation ... | 06/12/2007 |
| 7177520 | System and method of timecode repair and synchronization in MPEG streams A method, apparatus and article of manufacture is provided for processing a previously encoded MPEG video high-resolution (HR) file and corresponding proxy file, for frame accurate timecode repair and synchronization of individual video frames of the HR and proxy fi... | 02/13/2007 |
| 7054887 | Method and system for object replication in a content management system A system and method in accordance with the present invention provides for replication in a content management system. Replication is provided by utilizing the library server to track the objects to be replicated within the system. The replication is accomplished by ... | 05/30/2006 |
| 7015469 | Electron holography method An inline electron holograph method for observing a specimen with a transmission electron microscope having an electron gun, a collimating lens system, two spaced objective lenses, a biprism, and an imaging means comprises the steps of: with the first objective lens... | 03/21/2006 |
| 7016971 | Congestion management in a distributed computer system multiplying current variable injection rate with a constant to set new variable injection rate at source node A distributed computer system includes links and routing devices coupled between the links and routing frames between the links. Each of the routing devices includes a congestion control mechanism for detecting congestion at the routing device and responding to dete... | 03/21/2006 |
| 6876557 | Unified SRAM cache system for an embedded DRAM system having a micro-cell architecture A unified SRAM cache system is provided incorporated several SRAM macros of an embedded DRAM (eDRAM) system and their functions. Each incorporated SRAM macro can be independently accessed without interfering with the other incorporated SRAM macros within the unified... | 04/05/2005 |
| 6724225 | Logic circuit for true and complement signal generator A MOSFET logic circuit for performing a logic AND operation is presented including three transistors, wherein at least two input signals are provided to the circuit and an output signal indicative of an AND operation performed on a first and second input signal of t... | 04/20/2004 |
| 6714476 | Memory array with dual wordline operation A DRAM array is provided capable of being interchanged between single-cell and twin-cell array operation for storing data in a single-cell or a twin-cell array format, respectively. Preferably, the DRAM array is operated in the single-cell array format during one op... | 03/30/2004 |
| 6713791 | T-RAM array having a planar cell structure and method for fabricating the same A T-RAM array having a planar cell structure is presented. The T-RAM array includes n-MOS and p-MOS support devices which are fabricated by sharing process implant steps with T-RAM cells of the T-RAM array. A method is also presented for fabricating the T-RAM array ... | 03/30/2004 |
| 6682786 | Liquid crystal display cell having liquid crystal molecules in vertical or substantially vertical alignment A liquid crystal display cell having liquid crystal molecules positioned in a vertical or a substantially vertical alignment is provided. The liquid crystal display cell includes at least two substantially homogeneous fluorinated alignment layers disposed... | 01/27/2004 |
| 6683805 | Suppression of leakage currents in VLSI logic and memory circuits An SRAM system is provided having an array of SRAM cells including at least one circuit receiving a first power voltage and a power control circuit for supplying a second power voltage to at least one selected circuit of the at least one circuit. The syst... | 01/27/2004 |
| 6675130 | System and method of using a plurality of sensors for determining an individual's level of productivity A system is provided having a plurality of sensors for affixing to a person's torso, hands, feet, head, etc. The function of each sensor is to determine the distance between itself and the other sensors to ascertain the distance between the hands and feet... | 01/06/2004 |
| 6665642 | Transcoding system and method for improved access by users with special needs A system and method for providing transformed web pages to users with special needs is presented. In one aspect of the system and method, a Translator/Mediator Server is located between the user and the web site. The Translator/Mediator Server translates ... | 12/16/2003 |
| 6654414 | Video conferencing using camera environment panoramas Image data is communicated from a source system to a target system. At the source system, a background environment map is generated and communicated to the target system. The source system then captures a source image from position and field of view of a ... | 11/25/2003 |
| 6647008 | Method and system for sharing reserved bandwidth between several dependent connections in high speed packet switching networks A method for establishing a network connection through a link issuing from a physical port is disclosed. The link has an aggregation of connections. The network connection has a required capacity. The method first computes, from mean bit rates of the aggr... | 11/11/2003 |
| 6639488 | MEMS RF switch with low actuation voltage Disclosed is a capacitive electrostatic MEMS RF switch comprised of a lower electrode that acts as both a transmission line and as an actuation electrode. Also, there is an array of one or more fixed beams above the lower electrode that is connected to gr... | 10/28/2003 |
| 6634001 | Remote monitoring of computer programs Systems and methods for remotely monitoring the execution of computer programs are provided. Monitoring instructions are added the computer program so that during execution of the program, data may be collected regarding the program execution. The collect... | 10/14/2003 |
| 6631503 | Temperature programmable timing delay system The present invention provides a temperature programmable timing delay system utilizing circuitry for generating a band-gap reference and for sensing the on-chip temperature of an integrated circuit chip. The circuitry outputs the sensed temperature as a ... | 10/07/2003 |
| 6631141 | Methods, systems and computer program products for selecting an aggregator interface Methods, systems and computer program products are provided for which associate physical links of a network device to aggregator ports of the network device where there are more physical links of the network device capable of aggregation than aggregator p... | 10/07/2003 |
| 6627924 | Memory system capable of operating at high temperatures and method for fabricating the same A memory system having a plurality of T-RAM cells arranged in an array is presented where each T-RAM cell has dual vertical devices and is fabricated over a SiC substrate. Each T-RAM cell has a vertical thyristor and a vertical transfer gate. The top surf... | 09/30/2003 |
| 6621294 | Pad system for an integrated circuit or device The present invention provides a pad system for an integrated circuit or device. The pad system includes logic circuitry having at least one pad input terminal for connecting to at least one pad and at least two output terminals for connecting to the at l... | 09/16/2003 |
| 6617690 | Interconnect structures containing stress adjustment cap layer Novel interconnect structures possessing a relatively low internal stress and dielectric constant for use in semiconductor devices are provided herein. The novel interconnect structures comprise a first layer having a coefficient of thermal expansion grea... | 09/09/2003 |
| 6618704 | System and method of teleconferencing with the deaf or hearing-impaired A system and method is provided for real time teleconferencing, where one of the participants is deaf or hearing-impaired. In one aspect of the system and method, each participant has an Automatic Speech Recognition (ASR) system and a chat service system,... | 09/09/2003 |
| 6617702 | Semiconductor device utilizing alignment marks for globally aligning the front and back sides of a semiconductor substrate The present invention provides for globally aligning microelectronic circuit systems, such as communication devices and chips, fabricated on or bonded to the front and back sides of one or more substrates to provide for wireless communications between the... | 09/09/2003 |
| 6614714 | Semiconductor memory system having a data clock system for reliable high-speed data transfers A data clock system for a semiconductor memory system is provided for performing reliable high-speed data transfers. The semiconductor memory system includes a plurality of data banks configured for storing data, the plurality of data banks in operative c... | 09/02/2003 |
| 6611033 | Micromachined electromechanical (MEM) random access memory array and method of making same A micromachined electromechanical random access memory (MEMRAM) array is disclosed which includes a plurality of MEM memory cells, where each MEM memory cell has an MEM switch and a capacitor. The MEM switch includes a contact portion configured for movin... | 08/26/2003 |
| 6611678 | Device and method for trainable radio scanning A trainable radio scanner, including a station monitoring circuit to scan a plurality of radio frequencies and extract audio samples of a predetermined duration from each one of the plurality of radio frequencies having a signal strength above a reception... | 08/26/2003 |
| 6601093 | Address resolution in ad-hoc networking A method, system, and computer program product for resolving address information in an ad-hoc networking environment. Two indicators are defined to indicate whether (1) a device has a self-assigned (i.e. auto-configured) IP (Internet Protocol) address and... | 07/29/2003 |
| 6574127 | System and method for reducing noise of congested datalines in an eDRAM A dataline wiring structural system is provided for an eDRAM which suppresses coupling and switching noise associated with datalines by providing a plurality of metal levels upon which the datalines are positioned. Each of the datalines carrying a differe... | 06/03/2003 |
| 6563736 | Flash memory structure having double celled elements and method for fabricating the same A flash memory array having a plurality of bitlines, at least one wordline and a plurality of flash memory flash memory elements, wherein each flash memory element includes two transistors for storing two bits, and wherein each flash memory element is pos... | 05/13/2003 |
| 6556477 | Integrated chip having SRAM, DRAM and flash memory and method for fabricating the same A semiconductor memory system fabricated on one substrate is presented including an SRAM device, a DRAM device and a Flash memory device. In one embodiment the SRAM device is a high-resistive load SRAM device. In another embodiment the DRAM device is a de... | 04/29/2003 |
| 6552398 | T-Ram array having a planar cell structure and method for fabricating the same A T-RAM array having a planar cell structure is presented which includes a plurality of T-RAM cells. Each of the plurality of T-RAM cells is fabricated by using doped polysilicon to form a self-aligned diffusion region to create a low-contact resistance p... | 04/22/2003 |
| 6549450 | Method and system for improving the performance on SOI memory arrays in an SRAM architecture system The present invention provides an SOI SRAM architecture system which holds all the bitlines at a lower voltage level, for example, ground, or a fraction of Vdd, during array idle or sleep mode. Preferably, the bitlines are held at a voltage level approxim... | 04/15/2003 |
| 6545935 | Dual-port DRAM architecture system A dual-port, folded-bitline DRAM architecture system is presented which prioritizes two simultaneous access requests slated for a DRAM cell of a data array prior to performing at least one of the access requests to prevent affecting the integrity of the d... | 04/08/2003 |
| 6542973 | Integrated redundancy architecture system for an embedded DRAM An integrated redundancy eDRAM architecture system for an embedded DRAM macro system having a wide data bandwidth and wide internal bus width is disclosed which provides column and row redundancy for defective columns and rows of the eDRAM macro system. I... | 04/01/2003 |
| 6540674 | System and method for supervising people with mental disorders A system and method for supervising persons with a mental illness, the method comprising the steps of acquiring sensor data related to the person and the person's environment; tracking the acquired sensor data; and recognizing changes in the sensor data i... | 04/01/2003 |
| 6539434 | UOWE's retry process in shared queues environment An UOWE is created to represent a message which is put out to the coupling facility. If it is a committed message and the PUT failed for some reason, the UOWE is flagged for "retry". These retry UOWEs will accumulate over time. The retry logic analyzes ea... | 03/25/2003 |
| 6531911 | Low-power band-gap reference and temperature sensor circuit A combined low-voltage, low-power band-gap reference and temperature sensor circuit is provided for providing a band-gap reference parameter and for sensing the temperature of a chip, such as an eDRAM memory unit or CPU chip, using the band-gap reference ... | 03/11/2003 |
