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| Number | Title | Issue Date |
| 6011283 | Pillar emitter for BiCMOS devices A monolithic semiconductor device includes a field effect transistor and a bipolar junction transistor with a pillar emitter structure. The pillar structure raises the BJT emitter above the surface of a trenched base. Ions implanted into the base trench d... | 01/04/2000 |
| 5793410 | Video pedestal network An architecture for distributing digital information to subscriber units wherein selection from among multiple digital services is accomplished by transmitting a tuning command from a subscriber unit to an intermediate interface. The intermediate interfac... | 08/11/1998 |
| 5594765 | Interleaved and sequential counter A counter system has a first counter seeded by several input signals and a second counter seeded by at least a first output from the first counter. A selection signal is input to the second counter to select the use of either an interleaved count sequence... | 01/14/1997 |
| 5584028 | Method and device for processing multiple, asynchronous interrupt signals A device and method for processing a plurality of asynchronous interrupt signals provided to respective primary registers. The first provided of the signals is stored in a primary register. The primary registers are then closed to subsequently provided si... | 12/10/1996 |
| 5574851 | Method for performing on-line reconfiguration of a disk array concurrent with execution of disk I/O operations An architecture for on-line reconfiguration on a RAID level 0, 1, 2, 3, 4 or 5 disk array. This architecture allows the computer system to perform reconfiguration of the disk array transparently, with disk I/O operations being performed concurrently with ... | 11/12/1996 |
| 5559473 | Multi-range voltage controlled oscillator A circuit design extending the range and linearizing the transfer characteristic of a fast voltage controlled oscillator (VCO). In addition, a multi-range VCO is described. Range extension is achieved by modifying the delay cell of a current controlled ri... | 09/24/1996 |
| 5550986 | Data storage device matrix architecture A data storage system comprising a matrix of intelligent storage nodes interconnected to communicate with each other via a network of busses. The network of busses includes a plurality of first busses for conducting data from and to a corresponding plural... | 08/27/1996 |
| 5545440 | Method and apparatus for polymer coating of substrates A process for coating a surface of a substrate with a polymer material. The process includes heating a polymer to a preselected temperature such that the polymer, if solid, is in a liquid state or if liquid in a less viscous state to form a polymer soluti... | 08/13/1996 |
| 5543361 | Process for forming titanium silicide local interconnect A process for forming a titanium silicide local interconnect between electrodes separated by a dielectric insulator on an integrated circuit. A first layer of titanium is formed on the insulator, and a layer of silicon is formed on the titanium. The silic... | 08/06/1996 |
| 5541548 | Analog output driver for gate arrays The invention concerns an analog amplifier constructed using digital transistors. The digital transistors are those contained in a gate array, and which are used for fabrication of digital devices. The analog amplifier includes an invertor, which contains... | 07/30/1996 |
| 5536968 | Polysilicon fuse array structure for integrated circuits A programmable read only memory (PROM) including an array of polysilicon fuse elements. The fuse array is formed within a semiconductor substrate including first and second patterned signal layers electrically insulated from one another. Each polysilicon ... | 07/16/1996 |
| 5533190 | Method for maintaining parity-data consistency in a disk array A method for assuring consistency between data and parity in a disk array system following a reset or a power failure condition which interrupts the execution of write I/O operations. The method includes the steps of: examining drive activities to identif... | 07/02/1996 |
| 5528447 | 5-volt tolerant bi-directional i/o pad for 3-volt-optimized integrated circuits In an electronic IC package, an I/O PAD circuit design which protects 3 Volt optimized I/O functional circuits from damage due to the application of external 5 Volt signals to the I/O PAD both while the functional circuit design is powered on and powered ... | 06/18/1996 |
| 5527872 | Electronic device with a spin-on glass dielectric layer There is provided electronic devices with dielectric layers obtained from boron-oxide doped, spin-on glass formulations which form glassy layers with high oxygen resistance. Suitable electronic devices include integrated circuits. With high oxygen resista... | 06/18/1996 |
| 5526310 | Memory with latched output The invention concerns Random-Access Memory (RAM). In many types of RAM currently available, the data on the RAM's output lines can change (or, at least, is no longer guaranteed valid) after the address applied to the RAM changes. The invention maintains ... | 06/11/1996 |
| 5521834 | Method and apparatus for calculating dynamic power dissipation in CMOS integrated circuits A method and apparatus for approximating power dissipation using a computer-assisted engineering (CAE) system. Initially, a determination is made of the capacitive load for each cell in a netlist for the CMOS circuit, preferably from cell library data she... | 05/28/1996 |
| 5521640 | Color image array scanner with high resolution monochrome mode A solid-state array scanner with a color filter at each pixel sensor is provided to accomplish color scanning of color images with a set of pixels sensors for each color pixel. In addition, a scaler device is provided for selectively scaling the output pi... | 05/28/1996 |
| 5521476 | CMOS disk drive motor control circuit having back-EMF blocking circuitry A CMOS disk drive motor control circuit which has back-EMF blocking circuitry for preventing the back-EMF from being dissipated when power is removed from the disk drive motor. The back-EMF provides an alternate power source for parking the read/write hea... | 05/28/1996 |
| 5519355 | High speed boundary scan multiplexer An input cell for a semiconductor chip having an I/O region proximate the edge of the chip and a core region located inside the I/O region. The input cell is located in the I/O region and includes an input pad for receiving an input signal and a multiplex... | 05/21/1996 |
| 5519310 | Voltage-to-current converter without series sensing resistor A voltage controlled current source including feedback circuitry which eliminates the need for a current sensing resistor in series with the output voltage controlled current source. The feedback circuit includes circuitry for generating a reference curre... | 05/21/1996 |
| 5516718 | Method of making BI-CMOS integrated circuit having a polysilicon emitter The invention concerns a BI-CMOS process, in which Field-Effect Transistors (FETs) and Bipolar Junction Transistors (BJTs) are manufactured on a common substrate. In several processing steps, FET structures are formed simultaneously with BJT structures. F... | 05/14/1996 |
| 5506968 | Terminating access of an agent to a shared resource when a timer, started after a low latency agent requests access, reaches a predetermined value A method and apparatus for very low, in some case even zero, data latency accesses to a shared resource for devices such as disk drives and their channel formatting agents. The method and apparatus together will controllably terminate any non-low-latency ... | 04/09/1996 |
| 5504785 | Digital receiver for variable symbol rate communications A digital receiver includes a tuner and a demodulator that obtains the baseband signal carried in a received analog signal. A first sampler operates at a preselected fixed sampling rate asynchronous with the baseband component to produce a first sampler o... | 04/02/1996 |
| 5497343 | Reducing the number of carry-look-ahead adder stages in high-speed arithmetic units, structure and method A carry-look-ahead adder for adding an addend and an augend and generating a final sum. The addend, augend, and final sum are binary numbers, each having a plurality of bits. Bits of the same order in the addend and the augend are organized into columns. ... | 03/05/1996 |
| 5497027 | Multi-chip module packaging system A three dimensional logic cube comprises a base plate having two vertically mounted backplanes attached thereto. A plurality of horizontally stacked substrates are coupled by connectors to the backplanes, with enough clearance between adjacent substrates ... | 03/05/1996 |
| 5491429 | Apparatus for reducing current consumption in a CMOS inverter circuit A method and system for reducing pass-through current. The amount of simultaneous current flow through p-channel and n-channel devices of a CMOS inverter is reduced. This results in an increase in the power efficiency of CMOS oscillators, inverters, gates... | 02/13/1996 |
| 5488249 | Differential analog transistors constructed from digital transistors The invention concerns approaches to interconnecting individual field-effect transistors (FETs) in integrated circuits (ICs), in order to provide a larger, composite transistor. In one approach, the individual FETs are positioned symmetrically about centr... | 01/30/1996 |
| 5487160 | Concurrent image backup for disk storage system A disk drive within a disk array is utilized to capture the original image of data blocks that are updated, i.e., written over, through normal array processes during backup operations. The method captures original data images in a manner that allows the a... | 01/23/1996 |
| 5481207 | High speed, low power input/output circuit for a multi-chip module An I/O transceiver circuit for use on each integrated circuit of a multi-chip module that controls the threshold voltage of the receiver portion and also controls the output resistance of the transmitter portion. Control of the threshold voltage allows op... | 01/02/1996 |
| 5480840 | Multi-chip module with multiple compartments The present invention provides a multi-chip module having multiple compartments. Circuitry is arranged on a substrate in such a manner that circuit components requiring specific operating environments are located in discrete areas dedicated to accommodate... | 01/02/1996 |
| 5477198 | Extendible-range voltage controlled oscillator A circuit design extending the range and linearizing the transfer characteristic of a fast voltage controlled oscillator (VCO). In addition, a multi-range VCO is described. Range extension is achieved by modifying the delay cell of a current controlled ri... | 12/19/1995 |
| 5477180 | Circuit and method for generating a clock signal A clock generator circuit which produces a clock signal which may have an adjustable steady state duty cycle and which has the same frequency as a crystal frequency. The clock generator circuit includes a drive circuit coupled to the crystal which convert... | 12/19/1995 |
| 5472488 | Coating solution for forming glassy layers There is disclosed doped spin-on glass compositions such as boronoxide doped spin-on glass compositions with a high carbon content and silane adhesion promoter incorporated therein for use as coating layers on substrates such as silicon wafers.... | 12/05/1995 |
| 5471639 | Apparatus for arbitrating for a high speed direct memory access bus A high speed direct memory access (DMA) sub-system of a microprocessor system provides data interfaces between a high speed peripheral bus, such as a small computer system interface (SCSI) bus, and a DMA random access memory (RAM) to provide the data band... | 11/28/1995 |
| 5469082 | Peripheral component interfacing system with bus voltage/logic supply comparison means Voltage levels of an external bus are sampled with results stored to adjust both an output driver and input receiver. The resulting logic signal levels for the input/output (I/O) interface are maintained within acceptable ranges of the standard I/O signal... | 11/21/1995 |
| 5466614 | Structure and method for remotely measuring process data A method and structure for sensing data such as temperature with respect to objects such as silicon wafers undergoing fabrication or other processes involve the use of a monitor element of material and configuration similar to that of the objects being pr... | 11/14/1995 |
| 5463352 | Supply voltage tolerant phase-locked loop circuit A phase-locked loop design is provided that can operate at a plurality of dissimilar supply voltages. By adjusting the frequency range of a PLL based on the power supply voltage, the same PLL design can operate at different supply voltages.... | 10/31/1995 |
| 5459501 | Solid-state ink-jet print head An ink-jet print head comprises an ink drive unit formed on a first substrate and an ink reservoir unit formed on a second substrate. The ink drive unit includes a thin film piezoelectric transducer formed on one side of the substrate. The reservoir unit ... | 10/17/1995 |
| 5457434 | Integrated circuit oscillator with high voltage feedback network An oscillator circuit having an amplifier and feedback loop multiplies a generated signal by appropriate selection of capacitance ratios in the feedback loop. In order to isolate this multiplied, high voltage signal, a voltage divider is used to isolate t... | 10/10/1995 |
| 5455913 | System and method for transferring data between independent busses A system and method for transferring a designated number d of data bytes between first and second data busses. The system includes a data buffer connected between the busses, a full counter, a partial counter, and decode logic connected to the counters. T... | 10/03/1995 |
