William F. Semple, a dentist, was awarded the first US Patent on chewing gum in 1869. His recipe contained powdered chalk.
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| Number | Title | Issue Date |
| 8164195 | Pad structure of semiconductor integrated circuit apparatus A pad structure of a semiconductor integrated circuit apparatus includes a semiconductor substrate upon which circuit patterns forming a device are disposed, a pad disposed on an uppermost part of the semiconductor substrate, and a plurality of fixing parts, each di... | 04/24/2012 |
| 8154326 | Power control circuit, method of controlling power control circuit, and DLL circuit including power control circuit A power control circuit includes a check unit that receives a reference clock and generates a check signal for cyclically activating a feedback loop of a DLL circuit, a phase detecting unit that detects a phase difference between the reference clock and a feedback c... | 04/10/2012 |
| 8149953 | Data receiver of semiconductor integrated circuit A semiconductor integrated circuit equipped with an equalizer which has a circuit structure simpler than that of a related equalizer according to an FFE scheme or a DFE scheme and is capable of preventing a noise component from being amplified. The data receiver inc... | 04/03/2012 |
| 8149639 | Test apparatus of semiconductor integrated circuit and method using the same A test apparatus includes a test fuse unit for generating a test fuse signal in response to a test mode signal during a test time and generating a test fuse signals according to a fuse cutting after a termination of the test time, a combination signal generating uni... | 04/03/2012 |
| RE42976 | Semiconductor memory device with reduced data access time A memory device includes at least two cell blocks connected to a global bit line for outputting data in response to an instruction; at least one global bit line connection unit for selectively connecting the global bit line to each cell block under control of a cont... | 11/29/2011 |
| 8065550 | Digital delay locked loop circuit using mode register set A semiconductor memory device includes a mode register set for establishing information on a delay time, a delay time calculator for calculating an I/O path delay time of a data clock on a basis of a unit period of a system clock, and a delay locked clock generator ... | 11/22/2011 |
| 8050135 | Semiconductor memory device A semiconductor memory device includes: a first address buffer configured to be used in a test mode and a normal mode and to receive more addresses in the test mode than in the normal mode; and a second address buffer configured to be used in the normal mode and dis... | 11/01/2011 |
| 8050113 | Core voltage discharger and semiconductor memory device with the same A core voltage discharger is capable of adjusting an amount of a current discharged according to temperature. The discharger for decreasing a level of a predetermined voltage receives temperature information from an on die thermal sensor and discharges a different a... | 11/01/2011 |
| 8049262 | Semiconductor device with increased channel length and method for fabricating the same A semiconductor device includes a trench formed in a predetermined portion of a substrate and a first recess region beneath the trench. A field oxide layer is buried into both the trench and the first recess region. An active region is defined by the field oxide lay... | 11/01/2011 |
| 8035442 | Semiconductor device A semiconductor device including a pumping capacitor for inducing a high voltage, a switching circuit for transferring the high voltage induced by the pumping capacitor and a switching control circuit for controlling the switching circuit, wherein the switching cont... | 10/11/2011 |
| 8026557 | Semiconductor device with increased channel length and method for fabricating the same A semiconductor device with an increased channel length and a method for fabricating the same are provided. The semiconductor device includes: a substrate with an active region including a planar active region and a prominence active region formed on the planar acti... | 09/27/2011 |
| 8024628 | Apparatus and method for testing semiconductor memory device A semiconductor memory device for performing a reliability test includes a write driving block for generating a predetermined test voltage in a test mode and delivering a data inputted from an external circuit into the local I/O line pair during a data access operat... | 09/20/2011 |
| 8022409 | Semiconductor device with omega gate and method for fabricating a semiconductor device A substrate has an active region divided into storage node contact junction regions, channel regions and a bit line contact junction region. Device isolation layers are formed in the substrate isolating the active region from a neighboring active region Recess patte... | 09/20/2011 |
| 7957213 | Semiconductor memory apparatus A semiconductor memory apparatus includes: a compensation voltage input node; a core voltage generator configured to generate a core voltage using an external power source voltage and supply the core voltage to the compensation voltage input node; a compensation con... | 06/07/2011 |
| 7683684 | Power-down mode control apparatus and DLL circuit having the same A power-down mode control apparatus includes an internal power-down control block configured to receive a locking completion signal and to generate an internal power-down signal, which is toggled for a predetermined time; a noise check block configured to check occu... | 03/23/2010 |
| 7667330 | Semiconductor device for preventing inflow of high current from an input/output pad and a circuit for preventing inflow of high current thereof A semiconductor device includes an input/output pad, an input line of an internal circuit, and a plurality of metal lines formed on a lower portion of the input/output pad to have a buffer area overlapping with a plane area of the input/output pad, wherein one of an... | 02/23/2010 |
| 7656729 | Circuit and method for decoding column addresses in semiconductor memory apparatus A column address decoding circuit of a semiconductor memory apparatus includes a predecoder configured to combine a column address and a decoding test signal, thereby outputting a decoding address. A main decoder receives the decoding address, thereby outputting a p... | 02/02/2010 |
| 7643361 | Redundancy circuit capable of reducing time for redundancy discrimination A redundancy circuit in a semiconductor memory apparatus includes a comparison signal receiving unit to receive a plurality of comparison signals and a fuse enable signal in parallel, wherein the comparison signals are generated by comparing a plurality of row addre... | 01/05/2010 |
| 7619433 | Test circuit for a semiconductor integrated circuit A test circuit includes an output control section for generating a plurality of output buffer control signals in response to a plurality of data masking signals when a test mode signal is activated in read operation; and a data output buffer for masking some of data... | 11/17/2009 |
| 7580320 | Multi-port memory device There is provided a column repair technology of a semiconductor memory device. The semiconductor memory device includes: a normal bus connection part for transmitting/receiving data between global data buses and local data buses of each bank; a redundant bus connect... | 08/25/2009 |
| 7567117 | Data output clock signal generating apparatus and semiconductor integrated circuit with the same A data clock control apparatus includes a bias voltage generator configured to receive a plurality of test mode signals and a plurality of fuse signals and to generate a bias voltage to secure a predetermined potential difference from an external driving power suppl... | 07/28/2009 |
| 7507657 | Method for fabricating storage node contact in semiconductor device Disclosed is a method for fabricating a plurality of storage node contacts in a semiconductor device capable of minimizing an influence of a slurry residue and planarizing cruspidal patterns caused during a storage node contact isolation process. In accordance with ... | 03/24/2009 |
| 7505297 | Semiconductor memory device Provided are semiconductor design technologies, especially a bit line sense amplifier array of a semiconductor memory device. The semiconductor memory device includes a plurality of unit bit line sense amplifiers, a pull-up power line which is a power line of the pl... | 03/17/2009 |