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| Number | Title | Issue Date |
| 7990776 | Semiconductor memory device with optimum refresh cycle according to temperature variation A semiconductor memory device, which performs a refresh operation, includes: a temperature sensing unit for measuring temperature and for generating a temperature controlled voltage and a reference current based on the measured temperature; an analog-digital convers... | 08/02/2011 |
| 7937629 | Semiconductor memory apparatus having noise generating block and method of testing the same Disclosed are a semiconductor memory apparatus and a method of testing the same. The semiconductor memory apparatus includes memory banks, each of which includes a plurality of memory cells, a peripheral circuit unit that includes a plurality of circuit groups aroun... | 05/03/2011 |
| 7890785 | Apparatus and method of generating power-up signal of semiconductor memory apparatus An apparatus for generating a power-up signal of a semiconductor memory apparatus includes a first power-up signal generator that generates a first power-up signal to be activated on the basis of a comparison between a power supply voltage level supplied to the semi... | 02/15/2011 |
| 7888963 | Apparatus for controlling on-die termination An on-die termination control unit turns on/off a corresponding transistor according to a code signal and adjusts an on-die termination resistance so it is equal to an external resistance. An offset compensating unit detects an offset voltage from an output voltage ... | 02/15/2011 |
| 7881109 | Refresh circuit of semiconductor memory apparatus A refresh circuit of a semiconductor memory apparatus includes a bank active signal generator configured to selectively enable a plurality of bank active signals in response to a piled signal and disable the plurality of bank active signals in response to a pluralit... | 02/01/2011 |
| 7876628 | Data output circuit A data output circuit of a semiconductor memory apparatus includes: a control unit that outputs a first standby instruction signal, a second standby instruction signal, a first output instruction signal, and a second output instruction signal in response to an input... | 01/25/2011 |
| 7859924 | Apparatus for controlling test mode of semiconductor memory Disclosed is a test mode control apparatus of a semiconductor memory having a plurality of banks divided into first and second bank groups, a plurality of pads, and a test mode controller. The test mode controller outputs data to the pads from one of the first and s... | 12/28/2010 |
| 7602660 | Redundancy circuit semiconductor memory device A redundancy circuit in a semiconductor memory device comprises a fuse set controller configured to output a redundancy enable signal enabled according to applied address signals; a redundant selector; a spare redundant selector; and a spare fuse controller configur... | 10/13/2009 |
| 7595240 | Flash memory device with stacked dielectric structure including zirconium oxide and method for fabricating the same A dielectric structure disposed between a floating gate and a control gate of a flash memory device includes: a first dielectric layer; a third dielectric layer having a k-dielectric constant substantially the same as that of the first dielectric layer; and a second... | 09/29/2009 |
| 7563688 | Method for fabricating capacitor in semiconductor device A method for fabricating a capacitor in a semiconductor device includes forming a stack structure providing a plurality of open regions, the stack structure including an insulation layer and a hard mask pattern, forming a conductive layer over the stack structure an... | 07/21/2009 |
| 7527986 | Method for fabricating magnetic tunnel junction cell A method for fabricating a magnetic tunnel junction cell comprises forming an insulation layer with an opening, forming a first pattern including multiple layers of a first electrode pattern on a bottom surface and a sidewall of the opening and an anti-ferromagnetic... | 05/05/2009 |
| 7518175 | Semiconductor memory device and method for fabricating the same The present invention relates to a semiconductor memory device and a method for fabricating the same. The semiconductor memory device, including: a plurality of gate structures formed on a substrate; a contact junction region formed beneath the substrate disposed in... | 04/14/2009 |
| 7499363 | Semiconductor memory apparatus capable of reducing ground noise A semiconductor memory apparatus includes a bank that includes a core block where a memory cell array is disposed and a control block to drive the memory cell array, a ground power supply pad that is supplied with a ground power through a ground line, a switch that ... | 03/03/2009 |
| 7428286 | Duty cycle correction apparatus and method for use in a semiconductor memory device The present invention is directed to a duty cycle correction apparatus that can be implemented in a small size, and is capable of performing a phase lock more rapidly, and reducing the amount of current being consumed, and to a method thereof. The duty cycle correct... | 09/23/2008 |
| 7390611 | Photoresist coating composition and method for forming fine pattern using the same A photoresist coating composition that includes a compound represented by Formula 1 and an aqueous solvent, and a method for forming a fine pattern by coating the composition on a photoresist pattern to effectively reduce a size of a photoresist contact hole and a s... | 06/24/2008 |
| 7391663 | Structure and method for measuring the channel boosting voltage of NAND flash memory at a node between drain/source select transistor and adjacent flash memory cell Provided is a structure for testing a NAND flash memory including a string select transistor, a source select transistor, flash memory cells connected in series between the string select transistor and a source select transistor and a measurement pad coupled to a no... | 06/24/2008 |
| 7376035 | Semiconductor memory device for performing refresh operation and refresh method thereof A semiconductor memory device for performing a refresh operation comprises a memory cell array, a driving control unit, a word line driving unit, a sense amplifier driving unit and a sense amplifier. The memory cell array comprising a plurality of cells stores data.... | 05/20/2008 |
| 7366043 | Current reduction circuit of semiconductor device A current reduction circuit of a semiconductor device is disclosed which includes an enabling signal generator which outputs a predetermined enabling signal in association with a cell block in which a bridge has been formed between a word line and a bit line, and an... | 04/29/2008 |
| 7365406 | Non-uniform ion implantation apparatus and method thereof A non-uniform ion implantation apparatus comprises a wide ion beam generator configured to generate a plurality of wide ion beams to irradiate at least two regions on the entire area of a wafer, and a wafer rotating device configured to rotate the wafer in a predete... | 04/29/2008 |
| 7364837 | Method for pattern formation using photoresist cleaning solution Photoresist cleaning solutions are used to clean semiconductor substrates before or after an exposing step when photoresist patterns are formed. The cleaning solutions include H2O and a nonionic surfactant compound represented by Formula 1. By spraying th... | 04/29/2008 |
| RE40172 | Multi-bank testing apparatus for a synchronous dram A multi-bank testing apparatus for a synchronous DRAM, which allows all banks of the synchronous DRAM to simultaneously carry out their write and read operations in a test mode, thereby being capable of testing the entire bank in order to reduce the test time being ... | 03/25/2008 |
| RE40076 | Program circuit The program circuit according to the present invention can apply a program voltage to the only memory cells which are not programmed during a re-programming operation, thus, the present invention can be prevent a lowering of reliability of the memory cell due to a c... | 02/19/2008 |
| 7319342 | Data acceleration device and data transmission apparatus using the same A data acceleration device may include a pull-up driver for driving a pull-up in response to the signal level on a first node, a pull-down driver for driving a pull-down in response to the signal level on the first node, a first pull-up circuit for pull-up driving a... | 01/15/2008 |
| 7314825 | Method for forming contact plug of semiconductor device Disclosed is a method for fabricating a semiconductor device; and more particularly, to a method for fabricating a plurality of contact plugs capable of preventing a self-aligned contact (SAC) fail during forming a plurality of contact holes formed by using a SAC et... | 01/01/2008 |
| 7312647 | Memory device having a duty ratio corrector A memory device having a duty ratio corrector which can reduce power consumption by blocking current paths between output terminals and a ground terminal by applying input signals for turning off switching devices for generating an auxiliary voltage for correcting a... | 12/25/2007 |
| 7301201 | High voltage device having polysilicon region in trench and fabricating method thereof A high voltage device prevents or minimizes the lowering of a maximum operating voltage range. Bulk resistances of the drift regions are reduced by forming trenches within the drift regions and filling the trenches with conductive polysilicon layers. The polysilicon... | 11/27/2007 |
| 7301186 | Metal oxide semiconductor transistor and method for manufacturing the same A metal oxide semiconductor (MOS) transistor includes a source region having at least one source contact; a drain region having at least one drain contact; and a gate provided between the source region and the drain region, wherein the number of source contacts incl... | 11/27/2007 |
| 7289251 | Image sensor An image sensor is disclosed, in which the image sensor changes the diameter of a lens from the center area of a chip to an edge thereof to obtain uniform sensitivity as a whole. The image sensor includes a plurality of light-receiving portions for converting a sign... | 10/30/2007 |
| 7268085 | Method for fabricating semiconductor device The present invention relates to a method for forming a storage node contact of a semiconductor device. The method includes the steps of: depositing sequentially a conductive layer, a nitride layer and a polysilicon layer on a substrate having an insulating structur... | 09/11/2007 |
| 7268041 | Method of forming source contact of flash memory device The present invention relates to a method of forming a source contact of a flash memory device. According to the present invention, the method includes the steps of forming a first interlayer insulating film on a semiconductor substrate in which first junction regio... | 09/11/2007 |
| 7265042 | Method for fabricating semiconductor device with gate spacer The present invention relates to a method for fabricating a semiconductor device with gate spacers. The method includes the steps of: forming a plurality of gate structures on a substrate; forming an insulation layer on the gate structures and the substrate; and etc... | 09/04/2007 |
| 7265039 | Method for fabricating semiconductor device with improved refresh time The present invention relates to a method for fabricating a semiconductor device with improved refresh time. The method includes the steps of: forming a plurality of gate lines on a substrate; forming a plurality of cell junctions by ion-implanting a first dopant wi... | 09/04/2007 |
| 7257037 | Redundancy circuit in semiconductor memory device A redundancy circuit in a semiconductor memory device comprises a fuse set controller configured to output a redundancy enable signal enabled according to applied address signals; a redundant selector; a spare redundant selector; and a spare fuse controller configur... | 08/14/2007 |
| 7250341 | Flash memory device having poly spacers A non-volatile memory device includes a substrate having a first active region and a second active region. A first floating gate is provided over the first active region and having an edge, the first floating gate being made of a conductive material. A first spacer ... | 07/31/2007 |
| 7230875 | Delay locked loop for use in synchronous dynamic random access memory A delay locked loop (DLL) for compensating for a skew in a synchronous dynamic random access memory includes: a delay model means for delaying an external clock signal by the skew to generate a delayed clock signal; a control unit, in response to the external clock ... | 06/12/2007 |
| 7227210 | Ferroelectric memory transistor with highly-oriented film on gate insulator A method for fabricating a non-volatile memory device. The method includes providing a substrate, e.g., silicon. The method also includes forming an oxide layer overlying the substrate; and forming a buffer layer overlying the oxide layer. A ferroelectric material i... | 06/05/2007 |
| 7226829 | Method for fabricating semiconductor device The present invention is related to a method for forming a storage node of a semiconductor device. The method includes the steps of: (a) forming a plurality of bit line patterns, each including a wire and a hard mask sequentially stacked on a surface of a substrate ... | 06/05/2007 |
| 7224179 | Apparatus for adjusting slew rate in semiconductor memory device and method therefor The present invention relates to an apparatus for adjusting a slew rate of a data signal outputted by a signal from an external circuit in a semiconductor memory device and a method therefor. The apparatus includes: a slew rate control signal generation block for ou... | 05/29/2007 |
| 7200039 | Flash memory device with improved erase function and method for controlling erase operation of the same The present patent relates to flash memory devices with improved erase function, and method of controlling an erase operation of the same. According to the present patent, the flash memory device includes memory cell blocks, each having a plurality of memory cells s... | 04/03/2007 |
| 7196949 | Semiconductor memory device with reduced skew on data line A semiconductor memory device including: a plurality of read sense amplifiers for amplifying an output data of a memory cell; a plurality of read delay controllers for delaying an output data of the read sense amplifier by a predetermined time; a plurality of read l... | 03/27/2007 |
