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In 1879, Auguste Bartholdi received design patent number 11,023 titled "Design for a Statue". It was for the Statue of Liberty.
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| Number | Title | Issue Date |
| 8184494 | Cell inferiority test circuit A cell inferiority test circuit includes a compression data generator configured to compress selected data in response to selection signals and to generate compression data including information about cell inferiority, a strobe signal delayer configured to delay a s... | 05/22/2012 |
| 8183112 | Method for fabricating semiconductor device with vertical channel A method for fabricating a semiconductor device with a vertical channel includes providing a substrate over which a hard mask pattern is formed, forming pillars over the substrate using the hard mask pattern thereby forming a resultant structure, forming an insulati... | 05/22/2012 |
| 8174879 | Biosensor and sensing cell array using the same A biosensor and a sensing cell array using a biosensor are disclosed. Adjacent materials containing a plurality of different ingredients are analyzed to determine the ingredients based on their magnetic susceptibility or dielectric constant. A sensing cell array inc... | 05/08/2012 |
| 8169048 | Isolation structure in a memory device An isolation structure in a memory device and a method for fabricating the isolation structure. In the method, a first trench is formed in a cell region of a semiconductor substrate and a second trench in a peripheral region of the semiconductor substrate. A liner l... | 05/01/2012 |
| 8168491 | Method for fabricating dual poly gate in semiconductor device A method for fabricating a dual poly gate in a semiconductor device, comprising: forming a gate insulation layer and a polysilicon layer on a semiconductor substrate that defines a first region and a second region; implanting first and second conductive type impurit... | 05/01/2012 |
| 8168448 | Ferroelectric register, and method for manufacturing capacitor of the same The present invention discloses a ferroelectric register and a method for manufacturing a capacitor of the same. The ferroelectric register is configured to reduce probability of data storage failure due to a weak state capacitor, by connecting a plurality of capaci... | 05/01/2012 |
| 8165263 | Counting circuit and address counter using the same A counting circuit includes first to fifth flip-flops (FFs) and a logic operation unit. Each of the first to fourth FFs has an initial value based on a preset control signal input through a 4-bit set terminal. Each of the first to fourth FFs receives a signal at a c... | 04/24/2012 |
| 8164143 | Semiconductor device A method for fabricating a semiconductor device comprises: performing a thermal process to expanding a local doped region formed between gate patterns on a semiconductor substrate; and etching a central region of an expanded local doped region so that the expanded l... | 04/24/2012 |
| 8163646 | Interconnection wiring structure of a semiconductor device and method for manufacturing same A method for manufacturing an interconnection wiring structure of a semiconductor device includes forming an isolation region, which arranges active regions in a diagonal direction, in a semiconductor substrate; forming first damascene trenches, which open upper por... | 04/24/2012 |
| 8163627 | Method of forming isolation layer of semiconductor device A method of forming an isolation layer of a semiconductor device is disclosed herein, the method comprising the steps of providing a semiconductor substrate in which a tunnel insulating layer and a charge storage layer are formed on an active area and a trench is fo... | 04/24/2012 |
| 8163614 | Method for forming NAND typed memory device A method for fabricating a NAND type flash memory device includes defining a select transistor region and a memory cell region in a semiconductor substrate, forming a tunnel insulating layer, a floating gate conductive layer, and a dielectric layer over a semiconduc... | 04/24/2012 |
| 8163446 | Method for manufacturing photomask using self-assembled molecule layer A method for fabricating a photomask using a self-assembled molecule layer, comprising: forming, on a transparent substrate, a stacked structure of a phase shift pattern and a light shielding pattern over the phase shift pattern, the stacked structure exposing a por... | 04/24/2012 |
| 8163445 | Extreme ultraviolet mask and method for fabricating the same An EUV mask comprises a multi-reflecting layer is formed over a substrate and reflecting EUV light; an absorber layer pattern defining a sidewall formed over the multi-reflecting layer formed and selectively exposing a region of the multi-reflecting layer; and a ref... | 04/24/2012 |
| 8163190 | Method for fabricating a fine pattern In a method for fabricating a fine pattern, a target layer to be patterned is formed on a semiconductor substrate. A sacrificial pattern is formed on the target layer. The sacrificial pattern includes first sacrificial patterns arranged at a first spacing, and secon... | 04/24/2012 |
| 8159883 | Semiconductor memory device having a block decoder for preventing disturbance from unselected memory blocks A semiconductor memory device can improve electrical properties by prohibiting a leakage current, which flows through a memory cell, in such a way as to turn off a drain select transistor, a source select transistor and a side transistor of an unselected memory cell... | 04/17/2012 |
| 8158305 | Photomask for extreme ultraviolet lithography and method for fabricating the same A method for fabricating a photomask for extreme ultraviolet lithography is provided. A reflection layer reflecting extreme ultraviolet light is formed over a transparent substrate having a main chip region and a frame region. A phase shifter pattern is formed over ... | 04/17/2012 |
| 8154949 | Burst termination control circuit and semiconductor memory device using the same cross-references to related application A burst termination control circuit includes: a pull-up unit for pulling up a first node in response to a burst termination signal, a latch unit for latching a signal of the first node, a buffer for generating a first termination control signal for stopping data out... | 04/10/2012 |
| 8153483 | Semiconductor device having a vertical transistor and method for manufacturing the same A semiconductor device having a vertical transistor comprises a silicon substrate; a drain region, a channel region and a source region vertically stacked on the silicon substrate; a buried type bit line formed under the drain region in the silicon substrate to cont... | 04/10/2012 |
| 8153447 | Nonvolatile ferroelectric perpendicular electrode cell, FeRAM having the cell and method for manufacturing the cell A nonvolatile ferroelectric perpendicular electrode cell comprises a ferroelectric capacitor and a serial PN diode switch. The ferroelectric capacitor includes a word line perpendicular electrode as a first electrode and a storage perpendicular electrode as a second... | 04/10/2012 |
| 8152029 | Pump dispenser with bypass back flow A dispensing apparatus is disclosed. The dispensing apparatus has a product container for holding the fluid; a chamber including a dispensing cylinder having an inlet and an outlet; an inlet check valve disposed at the inlet of the chamber, the inlet check valve bei... | 04/10/2012 |
| 8151222 | Method for decomposing designed pattern layout and method for fabricating exposure mask using the same A method for decomposing a designed pattern layout and a method for fabricating an exposure mask using the same. After the designed pattern layout is automatically decomposed to obtain a plurality of mask layouts, a problematic region is determined through simulatio... | 04/03/2012 |
| 8149642 | Semiconductor memory device A semiconductor memory device includes a first power switch for interrupting supply of a first power voltage to a first node in a standby mode, and a second power switch connected between the first node and a second node applied with a second power voltage. ... | 04/03/2012 |
| 8148267 | Method of forming isolation layer of semiconductor memory device A method of forming isolation layers of a semiconductor memory device. In accordance with an embodiment of the invention, a semiconductor substrate in which trenches are formed is provided. A first dielectric layer is formed over the semiconductor substrate includin... | 04/03/2012 |
| 8148231 | Method of fabricating capacitor A semiconductor device and a method of fabricating the same include an electrode having a nickel layer with impurities. The electrode having a nickel layer with impurities can be a gate electrode or a capacitor electrode. The electrode having a nickel layer with imp... | 04/03/2012 |
| 8143163 | Method for forming pattern of semiconductor device A method for manufacturing a semiconductor device comprises performing a CMP process using an oxide film as an etching barrier film to maintain a polysilicon layer having a large open area. A word line pattern, a DSL pattern, and a SSL pattern that are formed by a f... | 03/27/2012 |
| 8143160 | Method of forming a contact plug of a semiconductor device In a method of forming a contact plug of a semiconductor device, a nitride layer is prevented from being broken by forming a passivation layer over the nitride layer when contact holes are formed by etching an insulating layer between select lines formed over a semi... | 03/27/2012 |
| 8141005 | Apparatus for OPC automation and method for fabricating semiconductor device using the same An OPC automation apparatus and manufacturing method of a semiconductor device using the same, being capable of improving the fabrication yield of a semiconductor device by establishing a system and an OPC automation apparatus in which an engineer computer and a wor... | 03/20/2012 |
| 8138821 | High voltage pumping circuit A swing width control circuit and a high voltage pumping circuit using the same are disclosed. The swing width control circuit includes a swing width controller for receiving a first pumping signal having a first swing width and generating a second pumping signal ha... | 03/20/2012 |
| 8133818 | Method of forming a hard mask pattern in a semiconductor device In a method of forming a hard mask pattern in a semiconductor device, only processes for forming patterns having a row directional line shape and a column directional line shape on a plane are performed so that the hard mask patterns can be formed to define densely ... | 03/13/2012 |
| 8133547 | Photoresist coating composition and method for forming fine contact of semiconductor device A coating composition containing a coating base resin and a C4-C10 alcohol as a main solvent, and a method for forming a fine contact of a semiconductor device including the steps of preparing the coating composition, forming a photoresist film... | 03/13/2012 |
| 8130564 | Semiconductor memory device capable of read out mode register information through DQ pads A semiconductor memory device is provided that is capable of reading out mode register information stored in a register adapted for LPDDR2 (Low Power DDR2), through DQ pads. The semiconductor memory device includes a mode register control unit configured to receive ... | 03/06/2012 |
| 8130082 | RFID system including a programmable RF tag A radio frequency (RF) tag is provided with an antenna coil adapted and configured to wirelessly exchange data with a read/write terminal, a RF transmitting/receiving unit adapted and configured to modulate and demodulate data exchanged via the antenna coil, a proto... | 03/06/2012 |
| 8129251 | Metal-insulator-metal-structured capacitor formed with polysilicon A METAL-INSULATOR-METAL structured capacitor is formed with polysilicon instead of an oxide film as a sacrificial layer material that defines a storage electrode region. A MPS (Meta-stable Poly Silicon) process is performed to increase the surface area of the sacrif... | 03/06/2012 |
| 8129094 | Method for manufacturing a semiconductor device A spacer is formed on side and top portions of a photoresist pattern after a mask process is performed so that the spacer may be used as an etching mask. The spacer is formed using a polymer deposition layer which is a low temperature oxide or nitride that can be de... | 03/06/2012 |
| 8125828 | Page buffer circuit with reduced size and methods for reading and programming data with the same A page buffer circuit with reduced size and methods for reading and programming data is provided. In the reading operation, the page buffer circuit reads out a data bit by alternatively using a higher bit register or a lower bit register regardless of whether the da... | 02/28/2012 |
| 8124478 | Method for fabricating flash memory device having vertical floating gate A method for fabricating a flash memory device includes forming a control gate having a hollow donut shape over an insulation layer formed over a substrate. The method also includes forming an inter-poly dielectric of a spacer shape on an inner wall of the control g... | 02/28/2012 |
| 8120113 | Metal line in semiconductor device A metal line in a semiconductor device includes an insulation layer having trenches formed therein, a barrier metal layer formed over the insulation layer and the trenches, a metal layer formed over the barrier metal layer, wherein the metal layer fills the trenches... | 02/21/2012 |
| 8119475 | Method of forming gate of semiconductor device A method of forming a gate of a semiconductor device comprising providing a semiconductor substrate over which a gate insulating layer, a first conductive layer, a dielectric layer, and a second conductive layer are sequentially formed, the semiconductor substrate d... | 02/21/2012 |
| 8116155 | Apparatus for measuring data setup/hold time An apparatus for measuring data setup/hold time is capable of effectively measuring a setup/hold time of data, and includes a data generating unit for delaying an external clock signal according to counting signals and generating an internal clock signal and data si... | 02/14/2012 |
| 8111560 | Semiconductor memory device A semiconductor memory device includes a first sense amplifier which senses data on a first line pair and generates a first output signal; and a test unit which senses the data on a first line pair and transfers a second output signal to a second line in response to... | 02/07/2012 |
